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replica code working but failing lvs

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samuelkcrow
2022-09-07 19:32:25 -07:00
parent 3ef52789be
commit f1f18b3b54
2 changed files with 8 additions and 4 deletions
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compiler/modules/replica_bitcell_array.py
+3 -1
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@@ -84,7 +84,7 @@ class replica_bitcell_array(bitcell_base_array):
"""
# Bitcell array
self.bitcell_array = factory.create(module_type="bitcell_array",
column_offset=len(self.left_rbl),
column_offset=1 + len(self.left_rbl),
cols=self.column_size,
rows=self.row_size)
@@ -181,11 +181,13 @@ class replica_bitcell_array(bitcell_base_array):
# All wordlines including dummy and RBL
self.replica_array_wordline_names = []
self.replica_array_wordline_names.extend(["gnd"] * len(self.all_ports))
for bit in range(self.rbl[0]):
self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[bit]])
self.replica_array_wordline_names.extend(self.all_wordline_names)
for bit in range(self.rbl[1]):
self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[self.rbl[0] + bit]])
self.replica_array_wordline_names.extend(["gnd"] * len(self.all_ports))
for port in range(self.rbl[0]):
self.add_pin(self.rbl_wordline_names[port][port], "INPUT")