From f1f18b3b54b91cead43e2ab439790f54e4698349 Mon Sep 17 00:00:00 2001 From: samuelkcrow Date: Wed, 7 Sep 2022 19:32:25 -0700 Subject: [PATCH] replica code working but failing lvs --- compiler/modules/capped_bitcell_array.py | 8 +++++--- compiler/modules/replica_bitcell_array.py | 4 +++- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/compiler/modules/capped_bitcell_array.py b/compiler/modules/capped_bitcell_array.py index 7891c91b..9313dd9f 100644 --- a/compiler/modules/capped_bitcell_array.py +++ b/compiler/modules/capped_bitcell_array.py @@ -92,9 +92,11 @@ class capped_bitcell_array(bitcell_base_array): """ self.replica_bitcell_array = factory.create(module_type="replica_bitcell_array", - column_offset=1, cols=self.column_size, - rows=self.row_size) + rows=self.row_size, + rbl=self.rbl, + left_rbl=self.left_rbl, + right_rbl=self.right_rbl) # Dummy Row or Col Cap, depending on bitcell array properties col_cap_module_type = ("col_cap_array" if self.cell.end_caps else "dummy_array") @@ -164,7 +166,7 @@ class capped_bitcell_array(bitcell_base_array): self.capped_array_wordline_names = [] self.capped_array_wordline_names.extend(["gnd"] * len(self.col_cap_top.get_wordline_names())) - self.capped_array_wordline_names.extend(self.all_wordline_names) + self.capped_array_wordline_names.extend(self.all_wordline_names) # TODO: I think I need rblwls here too self.capped_array_wordline_names.extend(["gnd"] * len(self.col_cap_bottom.get_wordline_names())) self.add_pin_list(self.all_wordline_names, "INPUT") diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index acb03f2a..c67544ee 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -84,7 +84,7 @@ class replica_bitcell_array(bitcell_base_array): """ # Bitcell array self.bitcell_array = factory.create(module_type="bitcell_array", - column_offset=len(self.left_rbl), + column_offset=1 + len(self.left_rbl), cols=self.column_size, rows=self.row_size) @@ -181,11 +181,13 @@ class replica_bitcell_array(bitcell_base_array): # All wordlines including dummy and RBL self.replica_array_wordline_names = [] + self.replica_array_wordline_names.extend(["gnd"] * len(self.all_ports)) for bit in range(self.rbl[0]): self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[bit]]) self.replica_array_wordline_names.extend(self.all_wordline_names) for bit in range(self.rbl[1]): self.replica_array_wordline_names.extend([x if x not in self.gnd_wordline_names else "gnd" for x in self.rbl_wordline_names[self.rbl[0] + bit]]) + self.replica_array_wordline_names.extend(["gnd"] * len(self.all_ports)) for port in range(self.rbl[0]): self.add_pin(self.rbl_wordline_names[port][port], "INPUT")