Altering control logic for read ports and write ports, by including only read or write specific circuitry. Altering replica bitline layout to support multiport

compiler/tests/14_replica_bitline_test.py

@@ -51,6 +51,23 @@ class replica_bitline_test(openram_test):
         a = replica_bitline.replica_bitline(stages,fanout,rows)
         self.local_check(a)
         
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 1
+        OPTS.num_r_ports = 1
+        
+        stages=4
+        fanout=4
+        rows=13
+        debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
+        a = replica_bitline.replica_bitline(stages,fanout,rows)
+        self.local_check(a)
+
+        stages=8
+        rows=100
+        debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
+        a = replica_bitline.replica_bitline(stages,fanout,rows)
+        self.local_check(a)
+        
         globals.end_openram()
         
 # instantiate a copy of the class to actually run the test

compiler/tests/16_control_logic_test.py

@@ -24,7 +24,6 @@ class control_logic_test(openram_test):
         self.local_check(a)
         
         # check control logic for multi-port
-        # only layout for 1RW is supported at the moment
         OPTS.bitcell = "pbitcell"
         OPTS.replica_bitcell = "replica_pbitcell"
         OPTS.num_rw_ports = 1
@@ -34,6 +33,19 @@ class control_logic_test(openram_test):
         debug.info(1, "Testing sample for control_logic for multiport")
         a = control_logic.control_logic(num_rows=128)
         self.local_check(a)
+        
+        # Check write-only and read-only control logic
+        OPTS.num_rw_ports = 1
+        OPTS.num_w_ports = 1
+        OPTS.num_r_ports = 1
+        
+        debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
+        a = control_logic.control_logic(num_rows=128, port="w")
+        self.local_check(a)
+        
+        debug.info(1, "Testing sample for control_logic for multiport, only read control logic")
+        a = control_logic.control_logic(num_rows=128, port="r")
+        self.local_check(a)
 
         globals.end_openram()