Nwell fixes in pgates.

Fix minor PEP8 format fixes.
Fix nwell to be 55% of cell height.
Move contact in hierarchical decoder for DRC error.

compiler/modules/hierarchical_decoder.py

@@ -5,18 +5,14 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-from tech import drc
 import debug
 import design
-from math import log
-from math import sqrt
-from math import ceil
 import math
-import contact
 from sram_factory import factory
 from vector import vector
 from globals import OPTS
 
+
 class hierarchical_decoder(design.design):
     """
     Dynamically generated hierarchical decoder.
@@ -34,13 +30,12 @@ class hierarchical_decoder(design.design):
         self.cell_height = b.height
         self.rows = rows
         self.num_inputs = math.ceil(math.log(self.rows, 2))
-        (self.no_of_pre2x4,self.no_of_pre3x8)=self.determine_predecodes(self.num_inputs)
+        (self.no_of_pre2x4, self.no_of_pre3x8)=self.determine_predecodes(self.num_inputs)
 
         self.create_netlist()
         if not OPTS.netlist_only:
             self.create_layout()
 
-
     def create_netlist(self):
         self.add_modules()
         self.setup_netlist_constants()
@@ -308,7 +303,6 @@ class hierarchical_decoder(design.design):
             base= vector(-self.pre2_4.width, num * self.pre2_4.height)
 
         self.pre2x4_inst[num].place(base)
-
         
     def place_pre3x8(self,num):
         """ Place 3x8 predecoder to the left of the origin and above any 2x4 decoders """
@@ -321,7 +315,6 @@ class hierarchical_decoder(design.design):
 
         self.pre3x8_inst[num].place(offset)
 
-
     def create_row_decoder(self):
         """ Create the row-decoder by placing NAND2/NAND3 and Inverters
         and add the primary decoder output pins. """
@@ -329,7 +322,6 @@ class hierarchical_decoder(design.design):
             self.create_decoder_nand_array()
             self.create_decoder_inv_array()
 
-
     def create_decoder_nand_array(self):
         """ Add a column of NAND gates for final decode """
 
@@ -556,7 +548,7 @@ class hierarchical_decoder(design.design):
         """ Add a pin for each row of vdd/gnd which are must-connects next level up. """
 
         # The vias will be placed in the center and right of the cells, respectively.
-        xoffset = self.nand_inst[0].cx()
+        xoffset = self.nand_inst[0].rx()
         for num in range(0,self.rows):
             for pin_name in ["vdd", "gnd"]:
                 # The nand and inv are the same height rows...

compiler/modules/hierarchical_predecode.py

@@ -8,12 +8,11 @@
 import debug
 import design
 import math
-from tech import drc
 import contact
 from vector import vector
-from globals import OPTS
 from sram_factory import factory
 
+
 class hierarchical_predecode(design.design):
     """
     Pre 2x4 and 3x8 decoder shared code.
@@ -42,7 +41,7 @@ class hierarchical_predecode(design.design):
         self.add_nand(self.number_of_inputs)
         self.add_mod(self.nand)
 
-    def add_nand(self,inputs):
+    def add_nand(self, inputs):
         """ Create the NAND for the predecode input stage """
         if inputs==2:
             self.nand = factory.create(module_type="pnand2",
@@ -51,7 +50,7 @@ class hierarchical_predecode(design.design):
             self.nand = factory.create(module_type="pnand3",
                                        height=self.cell_height)
         else:
-            debug.error("Invalid number of predecode inputs: {}".format(inputs),-1)
+            debug.error("Invalid number of predecode inputs: {}".format(inputs), -1)
             
     def setup_layout_constraints(self):
 
@@ -89,7 +88,6 @@ class hierarchical_predecode(design.design):
                                                      names=decode_names,
                                                      length=self.height - 2*self.m1_width)
 
-        
     def create_input_inverters(self):
         """ Create the input inverters to invert input signals for the decode stage. """
         self.in_inst = []
@@ -266,7 +264,7 @@ class hierarchical_predecode(design.design):
         """ Add a pin for each row of vdd/gnd which are must-connects next level up. """
 
         # Find the x offsets for where the vias/pins should be placed
-        in_xoffset = self.in_inst[0].rx()
+        in_xoffset = self.in_inst[0].rx() + self.m1_space
         out_xoffset = self.inv_inst[0].lx() - self.m1_space
         for num in range(0,self.number_of_outputs):
             # this will result in duplicate polygons for rails, but who cares