squashed update of pex progress due to timezone error

compiler/modules/bank.py

@@ -75,8 +75,7 @@ class bank(design.design):
         self.bank_array_ll = self.offset_all_coordinates().scale(-1,-1)
         self.bank_array_ur = self.bitcell_array_inst.ur()
         self.bank_array_ul = self.bitcell_array_inst.ul()
-
-
+        
         self.DRC_LVS()
 
     def add_pins(self):
@@ -968,7 +967,7 @@ class bank(design.design):
         stage_effort_list += self.port_address.wordline_driver.determine_wordline_stage_efforts(wordline_cout,inp_is_rise)
         
         return stage_effort_list
-        
+
     def get_wl_en_cin(self):
         """Get the relative capacitance of all the clk connections in the bank"""
         #wl_en only used in the wordline driver.

compiler/modules/control_logic.py

@@ -789,7 +789,7 @@ class control_logic(design.design):
                                            layer="metal1",
                                            start=out_pin.center(),
                                            end=right_pos)
-
+        
 
 
     def route_supply(self):
@@ -847,7 +847,7 @@ class control_logic(design.design):
                            height=pin.height(),
                            width=pin.width())
                            
-
+    
     def get_delays_to_wl(self):
         """Get the delay (in delay units) of the clk to a wordline in the bitcell array"""
         debug.check(self.sram.all_mods_except_control_done, "Cannot calculate sense amp enable delay unless all module have been added.")