mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-07 03:20:39 +02:00
Merge branch 'add_wmask' into dev
This commit is contained in:
Matt Guthaus
@@ -121,7 +121,7 @@ class bank(design.design):
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self.route_column_address_lines(port)
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self.route_control_lines(port)
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if self.num_banks > 1:
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self.route_bank_select(port)
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self.route_bank_select(port)
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self.route_supplies()
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@@ -711,8 +711,9 @@ class bank(design.design):
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decoder_name = "addr_{}".format(row)
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addr_name = "addr{0}_{1}".format(port,addr_idx)
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self.copy_layout_pin(self.port_address_inst[port], decoder_name, addr_name)
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def route_port_data_in(self, port):
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""" Connecting port data in """
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@@ -720,6 +721,14 @@ class bank(design.design):
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data_name = "din_{}".format(row)
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din_name = "din{0}_{1}".format(port,row)
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self.copy_layout_pin(self.port_data_inst[port], data_name, din_name)
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if self.word_size is not None:
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for row in range(self.num_wmasks):
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wmask_name = "bank_wmask_{}".format(row)
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bank_wmask_name = "bank_wmask{0}_{1}".format(port, row)
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self.copy_layout_pin(self.port_data_inst[port], wmask_name, bank_wmask_name)
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def channel_route_bitlines(self, inst1, inst2, num_bits,
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inst1_bl_name="bl_{}", inst1_br_name="br_{}",
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+108
-37
@@ -109,7 +109,7 @@ class port_data(design.design):
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def route_layout(self):
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""" Create routing amoung the modules """
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""" Create routing among the modules """
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self.route_data_lines()
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self.route_layout_pins()
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self.route_supplies()
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@@ -123,7 +123,9 @@ class port_data(design.design):
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""" Route the bitlines depending on the port type rw, w, or r. """
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if self.port in self.readwrite_ports:
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# write_driver -> sense_amp -> (column_mux) -> precharge -> bitcell_array
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# (write_mask_and ->) write_driver -> sense_amp -> (column_mux ->) precharge -> bitcell_array
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self.route_write_mask_and_array_in(self.port)
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self.route_write_mask_and_array_to_write_driver(self.port)
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self.route_write_driver_in(self.port)
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self.route_sense_amp_out(self.port)
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self.route_write_driver_to_sense_amp(self.port)
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@@ -135,8 +137,10 @@ class port_data(design.design):
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self.route_sense_amp_to_column_mux_or_precharge_array(self.port)
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self.route_column_mux_to_precharge_array(self.port)
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else:
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# write_driver -> (column_mux ->) precharge -> bitcell_array
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self.route_write_driver_in(self.port)
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# (write_mask_and ->) write_driver -> (column_mux ->) precharge -> bitcell_array
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self.route_write_mask_and_array_in(self.port)
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self.route_write_mask_and_array_to_write_driver(self.port)
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self.route_write_driver_in(self.port)
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self.route_write_driver_to_column_mux_or_precharge_array(self.port)
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self.route_column_mux_to_precharge_array(self.port)
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@@ -298,23 +302,23 @@ class port_data(design.design):
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""" Placing Sense amp """
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self.sense_amp_array_inst.place(offset=offset, mirror="MX")
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def create_write_driver_array(self):
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""" Creating Write Driver """
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self.write_driver_array_inst = self.add_inst(name="write_driver_array{}".format(self.port),
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self.write_driver_array_inst = self.add_inst(name="write_driver_array{}".format(self.port),
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mod=self.write_driver_array)
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temp = []
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for bit in range(self.word_size):
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temp.append("din_{}".format(bit))
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for bit in range(self.word_size):
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for bit in range(self.word_size):
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if (self.words_per_row == 1):
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temp.append(self.bl_names[self.port]+"_{0}".format(bit))
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temp.append(self.br_names[self.port]+"_{0}".format(bit))
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temp.append(self.bl_names[self.port] + "_{0}".format(bit))
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temp.append(self.br_names[self.port] + "_{0}".format(bit))
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else:
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temp.append(self.bl_names[self.port]+"_out_{0}".format(bit))
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temp.append(self.br_names[self.port]+"_out_{0}".format(bit))
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temp.append(self.bl_names[self.port] + "_out_{0}".format(bit))
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temp.append(self.br_names[self.port] + "_out_{0}".format(bit))
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if self.write_size:
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for i in range(self.num_wmasks):
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@@ -326,10 +330,15 @@ class port_data(design.design):
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self.connect_inst(temp)
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def place_write_driver_array(self, offset):
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""" Placing Write Driver """
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self.write_driver_array_inst.place(offset=offset, mirror="MX")
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def create_write_mask_and_array(self):
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""" Creating Write Masks """
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""" Creating Write Mask AND Array """
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self.write_mask_and_array_inst = self.add_inst(name="write_mask_and_array{}".format(self.port),
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mod=self.write_mask_and_array)
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mod=self.write_mask_and_array)
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temp = []
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for bit in range(self.num_wmasks):
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@@ -341,10 +350,10 @@ class port_data(design.design):
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self.connect_inst(temp)
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def place_write_driver_array(self, offset):
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""" Placing Write Driver """
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self .write_driver_array_inst.place(offset=offset, mirror="MX")
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def place_write_mask_and_array(self, offset):
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""" Placing Write Mask AND array """
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self.write_mask_and_array_inst.place(offset=offset, mirror="MX")
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def compute_instance_offsets(self):
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"""
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@@ -356,41 +365,41 @@ class port_data(design.design):
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vertical_port_order.append(self.column_mux_array_inst)
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vertical_port_order.append(self.sense_amp_array_inst)
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vertical_port_order.append(self.write_driver_array_inst)
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vertical_port_order.append(self.write_mask_and_array_inst)
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# Add one column for the the RBL
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if self.port==0:
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x_offset = self.bitcell.width
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else:
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x_offset = 0
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vertical_port_offsets = 4*[None]
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vertical_port_offsets = 5 * [None]
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self.width = x_offset
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self.height = 0
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for i,p in enumerate(vertical_port_order):
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if p==None:
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for i, p in enumerate(vertical_port_order):
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if p == None:
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continue
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self.height += (p.height + self.m2_gap)
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self.width = max(self.width, p.width)
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vertical_port_offsets[i]=vector(x_offset,self.height)
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vertical_port_offsets[i] = vector(x_offset, self.height)
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# Reversed order
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self.write_mask_and_offset = vertical_port_offsets[4]
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self.write_driver_offset = vertical_port_offsets[3]
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self.sense_amp_offset = vertical_port_offsets[2]
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self.column_mux_offset = vertical_port_offsets[1]
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self.precharge_offset = vertical_port_offsets[0]
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# Shift the precharge left if port 0
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if self.precharge_offset and self.port==0:
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self.precharge_offset -= vector(x_offset,0)
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if self.precharge_offset and self.port == 0:
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self.precharge_offset -= vector(x_offset, 0)
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def place_instances(self):
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""" Place the instances. """
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# These are fixed in the order: write driver, sense amp, clumn mux, precharge,
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# These are fixed in the order: write mask ANDs, write driver, sense amp, column mux, precharge,
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# even if the item is not used in a given port (it will be None then)
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if self.write_mask_and_offset:
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self.place_write_mask_and_array(self.write_mask_and_offset)
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if self.write_driver_offset:
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self.place_write_driver_array(self.write_driver_offset)
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if self.sense_amp_offset:
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@@ -400,6 +409,7 @@ class port_data(design.design):
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if self.column_mux_offset:
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self.place_column_mux_array(self.column_mux_offset)
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def route_sense_amp_out(self, port):
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""" Add pins for the sense amp output """
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@@ -410,7 +420,8 @@ class port_data(design.design):
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offset=data_pin.center(),
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height=data_pin.height(),
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width=data_pin.width())
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def route_write_driver_in(self, port):
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""" Connecting write driver """
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@@ -418,7 +429,58 @@ class port_data(design.design):
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data_name = "data_{}".format(row)
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din_name = "din_{}".format(row)
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self.copy_layout_pin(self.write_driver_array_inst, data_name, din_name)
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def route_write_mask_and_array_in(self, port):
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""" Add pins for the write mask and array input """
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for bit in range(self.num_wmasks):
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wmask_in_name = "wmask_in_{}".format(bit)
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bank_wmask_name = "bank_wmask_{}".format(bit)
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self.copy_layout_pin(self.write_mask_and_array_inst, wmask_in_name, bank_wmask_name)
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def route_write_mask_and_array_to_write_driver(self,port):
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""" Routing of wdriver_sel_{} between write mask AND array and write driver array. Adds layout pin for write
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mask AND array output and via for write driver enable """
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inst1 = self.write_mask_and_array_inst
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inst2 = self.write_driver_array_inst
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loc = 0
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for bit in range(self.num_wmasks):
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# Bring write mask AND array output pin to port data level
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self.copy_layout_pin(inst1, "wmask_out_{0}".format(bit), "wdriver_sel_{0}".format(bit))
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wmask_out_pin = inst1.get_pin("wmask_out_{0}".format(bit))
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wdriver_en_pin = inst2.get_pin("en_{0}".format(bit))
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# The metal2 wdriver_sel_{} wire must hit the en_{} pin after the closest bitline pin that's right of the
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# the wdriver_sel_{} pin in the write driver AND array.
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if bit == 0:
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# When the write mask output pin is right of the bitline, the target is found
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while (wmask_out_pin.lx() + self.m2_pitch > inst2.get_pin("data_{0}".format(loc)).rx()):
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loc += 1
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length = inst2.get_pin("data_{0}".format(loc)).rx() + self.m2_pitch
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debug.check(loc<=self.num_wmasks,"Couldn't route the write mask select.")
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else:
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# Stride by the write size rather than finding the next pin to the right
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loc += self.write_size
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length = inst2.get_pin("data_{0}".format(loc)).rx() + self.m2_pitch
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beg_pos = wmask_out_pin.center()
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middle_pos = vector(length,wmask_out_pin.cy())
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end_pos = vector(length, wdriver_en_pin.cy())
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# Add via for the write driver array's enable input
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=end_pos)
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# Route between write mask AND array and write driver array
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self.add_wire(("metal1","via1","metal2"), [beg_pos, middle_pos, end_pos])
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def route_column_mux_to_precharge_array(self, port):
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""" Routing of BL and BR between col mux and precharge array """
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@@ -434,7 +496,6 @@ class port_data(design.design):
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self.connect_bitlines(inst1, inst2, self.num_cols)
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def route_sense_amp_to_column_mux_or_precharge_array(self, port):
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""" Routing of BL and BR between sense_amp and column mux or precharge array """
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inst2 = self.sense_amp_array_inst
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@@ -459,6 +520,7 @@ class port_data(design.design):
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self.channel_route_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size,
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inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name, inst1_start_bit=start_bit)
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def route_write_driver_to_column_mux_or_precharge_array(self, port):
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""" Routing of BL and BR between sense_amp and column mux or precharge array """
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inst2 = self.write_driver_array_inst
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@@ -481,10 +543,11 @@ class port_data(design.design):
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self.channel_route_bitlines(inst1=inst1, inst2=inst2, num_bits=self.word_size,
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inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name, inst1_start_bit=start_bit)
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def route_write_driver_to_sense_amp(self, port):
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""" Routing of BL and BR between write driver and sense amp """
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inst1 = self.write_driver_array_inst
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inst2 = self.sense_amp_array_inst
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@@ -508,13 +571,13 @@ class port_data(design.design):
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else:
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bit_offset=0
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for bit in range(self.num_cols):
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if self.precharge_array_inst:
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self.copy_layout_pin(self.precharge_array_inst, "bl_{}".format(bit+bit_offset), "bl_{}".format(bit))
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self.copy_layout_pin(self.precharge_array_inst, "br_{}".format(bit+bit_offset), "br_{}".format(bit))
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else:
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debug.error("Didn't find precharge arra.")
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debug.error("Didn't find precharge array.")
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def route_control_pins(self):
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""" Add the control pins: s_en, p_en_bar, w_en """
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@@ -527,7 +590,15 @@ class port_data(design.design):
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if self.sense_amp_array_inst:
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self.copy_layout_pin(self.sense_amp_array_inst, "en", "s_en")
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if self.write_driver_array_inst:
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self.copy_layout_pin(self.write_driver_array_inst, "en", "w_en")
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if self.write_mask_and_array_inst:
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for bit in range(self.num_wmasks):
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# Add write driver's en_{} pins
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self.copy_layout_pin(self.write_driver_array_inst, "en_{}".format(bit), "wdriver_sel_{}".format(bit))
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else:
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self.copy_layout_pin(self.write_driver_array_inst, "en", "w_en")
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if self.write_mask_and_array_inst:
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self.copy_layout_pin(self.write_mask_and_array_inst, "en", "w_en")
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def channel_route_bitlines(self, inst1, inst2, num_bits,
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@@ -49,7 +49,6 @@ class write_driver_array(design.design):
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self.width = self.columns * self.bitcell.width
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else:
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self.width = self.columns * self.driver.width
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self.height = self.driver.height
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self.place_write_array()
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@@ -63,9 +62,9 @@ class write_driver_array(design.design):
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for i in range(self.word_size):
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self.add_pin("bl_{0}".format(i), "OUTPUT")
|
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self.add_pin("br_{0}".format(i), "OUTPUT")
|
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if self.write_size != None:
|
||||
if self.write_size is not None:
|
||||
for i in range(self.num_wmasks):
|
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self.add_pin("en_{}".format(i), "INPUT")
|
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self.add_pin("en_{0}".format(i), "INPUT")
|
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else:
|
||||
self.add_pin("en", "INPUT")
|
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self.add_pin("vdd", "POWER")
|
||||
@@ -95,6 +94,7 @@ class write_driver_array(design.design):
|
||||
"br_{0}".format(index),
|
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"en_{0}".format(windex), "vdd", "gnd"])
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w+=1
|
||||
# when w equals write size, the next en pin can be connected since we are now at the next wmask bit
|
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if w == self.write_size:
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w = 0
|
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windex+=1
|
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@@ -107,13 +107,12 @@ class write_driver_array(design.design):
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||||
|
||||
def place_write_array(self):
|
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if self.bitcell.width > self.driver.width:
|
||||
driver_spacing = self.bitcell.width
|
||||
self.driver_spacing = self.bitcell.width
|
||||
else:
|
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driver_spacing = self.driver.width
|
||||
|
||||
self.driver_spacing = self.driver.width
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for i in range(0,self.columns,self.words_per_row):
|
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index = int(i/self.words_per_row)
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||||
base = vector(i * driver_spacing,0)
|
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index = int(i/self.words_per_row)
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||||
base = vector(i * self.driver_spacing, 0)
|
||||
self.driver_insts[index].place(base)
|
||||
|
||||
|
||||
@@ -149,15 +148,28 @@ class write_driver_array(design.design):
|
||||
self.add_layout_pin_rect_center(text=n,
|
||||
layer="metal3",
|
||||
offset=pin_pos)
|
||||
if self.write_size is not None:
|
||||
for bit in range(self.num_wmasks):
|
||||
en_pin = self.driver_insts[bit*self.write_size].get_pin("en")
|
||||
# Determine width of wmask modified en_pin with/without col mux
|
||||
wmask_en_len = self.words_per_row*(self.write_size * self.driver_spacing)
|
||||
if (self.words_per_row == 1):
|
||||
en_gap = self.driver_spacing - en_pin.width()
|
||||
else:
|
||||
en_gap = self.driver_spacing
|
||||
|
||||
self.add_layout_pin(text="en_{0}".format(bit),
|
||||
layer=en_pin.layer,
|
||||
offset=en_pin.ll(),
|
||||
width=wmask_en_len-en_gap,
|
||||
height=en_pin.height())
|
||||
else:
|
||||
self.add_layout_pin(text="en",
|
||||
layer="metal1",
|
||||
offset=self.driver_insts[0].get_pin("en").ll().scale(0,1),
|
||||
width=self.width)
|
||||
|
||||
|
||||
|
||||
self.add_layout_pin(text="en",
|
||||
layer="metal1",
|
||||
offset=self.driver_insts[0].get_pin("en").ll().scale(0,1),
|
||||
width=self.width,
|
||||
height=drc('minwidth_metal1'))
|
||||
|
||||
|
||||
|
||||
def get_w_en_cin(self):
|
||||
|
||||
@@ -16,8 +16,8 @@ from globals import OPTS
|
||||
|
||||
class write_mask_and_array(design.design):
|
||||
"""
|
||||
Array of tristate drivers to write to the bitlines through the column mux.
|
||||
Dynamically generated write driver array of all bitlines.
|
||||
Array of AND gates to turn write mask signal on only when w_en is on.
|
||||
The write mask AND array goes between the write driver array and the sense amp array.
|
||||
"""
|
||||
|
||||
def __init__(self, name, columns, word_size, write_size):
|
||||
@@ -34,29 +34,23 @@ class write_mask_and_array(design.design):
|
||||
self.num_wmasks = int(word_size / write_size)
|
||||
|
||||
self.create_netlist()
|
||||
# if not OPTS.netlist_only:
|
||||
# self.create_layout()
|
||||
if not OPTS.netlist_only:
|
||||
self.create_layout()
|
||||
|
||||
def create_netlist(self):
|
||||
self.add_modules()
|
||||
self.add_pins()
|
||||
# self.create_write_mask_array()
|
||||
self.create_and2_array()
|
||||
|
||||
|
||||
# def create_layout(self):
|
||||
#
|
||||
# if self.bitcell.width > self.driver.width:
|
||||
# self.width = self.columns * self.bitcell.width
|
||||
# else:
|
||||
# self.width = self.columns * self.driver.width
|
||||
#
|
||||
# self.height = self.driver.height
|
||||
#
|
||||
# self.place_write_array()
|
||||
# self.add_layout_pins()
|
||||
# self.add_boundary()
|
||||
# self.DRC_LVS()
|
||||
def create_layout(self):
|
||||
self.place_and2_array()
|
||||
spacing = self.wmask_en_len - self.and2.width
|
||||
self.width = (self.num_wmasks*self.and2.width) + ((self.num_wmasks-1)*spacing)
|
||||
self.height = self.and2.height
|
||||
self.add_layout_pins()
|
||||
self.add_boundary()
|
||||
self.DRC_LVS()
|
||||
|
||||
def add_pins(self):
|
||||
for bit in range(self.num_wmasks):
|
||||
@@ -68,28 +62,13 @@ class write_mask_and_array(design.design):
|
||||
self.add_pin("gnd","GROUND")
|
||||
|
||||
def add_modules(self):
|
||||
self.wmask = factory.create(module_type="dff_buf")
|
||||
#self.add_mod(self.wmask)
|
||||
dff_height = self.wmask.height
|
||||
|
||||
# Size the AND gate for the number of write drivers it drives, which is equal to the write size.
|
||||
# Assume stage effort of 3 to compute the size
|
||||
self.and2 = factory.create(module_type="pand2",
|
||||
size=4,
|
||||
height=dff_height)
|
||||
size=self.write_size/4.0)
|
||||
self.add_mod(self.and2)
|
||||
|
||||
|
||||
# def create_write_mask_array(self):
|
||||
# self.wmask_insts = {}
|
||||
# for bit in range(self.num_wmask):
|
||||
# name = "write_mask_{}".format(bit)
|
||||
# self.wmask_insts[bit] = self.add_inst(name=name,
|
||||
# mod=self.wmask)
|
||||
#
|
||||
# self.connect_inst(["wmask_{}".format(bit),
|
||||
# "bank_wmask_{}".format(bit),
|
||||
# "bank_wmask_bar_{}".format(bit),
|
||||
# "clk", "vdd", "gnd"])
|
||||
|
||||
def create_and2_array(self):
|
||||
self.and2_insts = {}
|
||||
for bit in range(self.num_wmasks):
|
||||
@@ -102,59 +81,84 @@ class write_mask_and_array(design.design):
|
||||
"vdd", "gnd"])
|
||||
|
||||
|
||||
# def place_write_array(self):
|
||||
# if self.bitcell.width > self.driver.width:
|
||||
# driver_spacing = self.bitcell.width
|
||||
# else:
|
||||
# driver_spacing = self.driver.width
|
||||
#
|
||||
# for i in range(0, self.columns, self.words_per_row):
|
||||
# index = int(i / self.words_per_row)
|
||||
# base = vector(i * driver_spacing, 0)
|
||||
# self.driver_insts[index].place(base)
|
||||
def place_and2_array(self):
|
||||
# Place the write mask AND array at the start of each write driver enable length.
|
||||
# This ensures the write mask AND array will be directly under the corresponding write driver enable wire.
|
||||
|
||||
# def add_layout_pins(self):
|
||||
# for i in range(self.word_size):
|
||||
# din_pin = self.driver_insts[i].get_pin("din")
|
||||
# self.add_layout_pin(text="data_{0}".format(i),
|
||||
# layer="metal2",
|
||||
# offset=din_pin.ll(),
|
||||
# width=din_pin.width(),
|
||||
# height=din_pin.height())
|
||||
# bl_pin = self.driver_insts[i].get_pin("bl")
|
||||
# self.add_layout_pin(text="bl_{0}".format(i),
|
||||
# layer="metal2",
|
||||
# offset=bl_pin.ll(),
|
||||
# width=bl_pin.width(),
|
||||
# height=bl_pin.height())
|
||||
#
|
||||
# br_pin = self.driver_insts[i].get_pin("br")
|
||||
# self.add_layout_pin(text="br_{0}".format(i),
|
||||
# layer="metal2",
|
||||
# offset=br_pin.ll(),
|
||||
# width=br_pin.width(),
|
||||
# height=br_pin.height())
|
||||
#
|
||||
# for n in ["vdd", "gnd"]:
|
||||
# pin_list = self.driver_insts[i].get_pins(n)
|
||||
# for pin in pin_list:
|
||||
# pin_pos = pin.center()
|
||||
# # Add the M2->M3 stack
|
||||
# self.add_via_center(layers=("metal2", "via2", "metal3"),
|
||||
# offset=pin_pos)
|
||||
# self.add_layout_pin_rect_center(text=n,
|
||||
# layer="metal3",
|
||||
# offset=pin_pos)
|
||||
#
|
||||
# self.add_layout_pin(text="en",
|
||||
# layer="metal1",
|
||||
# offset=self.driver_insts[0].get_pin("en").ll().scale(0, 1),
|
||||
# width=self.width,
|
||||
# height=drc('minwidth_metal1'))
|
||||
# This is just used for measurements, so don't add the module
|
||||
self.bitcell = factory.create(module_type="bitcell")
|
||||
self.driver = factory.create(module_type="write_driver")
|
||||
if self.bitcell.width > self.driver.width:
|
||||
self.driver_spacing = self.bitcell.width
|
||||
else:
|
||||
self.driver_spacing = self.driver.width
|
||||
|
||||
# def get_w_en_cin(self):
|
||||
# """Get the relative capacitance of all the enable connections in the bank"""
|
||||
# # The enable is connected to a nand2 for every row.
|
||||
# return self.driver.get_w_en_cin() * len(self.driver_insts)
|
||||
self.wmask_en_len = self.words_per_row * (self.write_size * self.driver_spacing)
|
||||
debug.check(self.wmask_en_len >= self.and2.width,
|
||||
"Write mask AND is wider than the corresponding write drivers {0} vs {1}.".format(self.and2.width,self.wmask_en_len))
|
||||
|
||||
for i in range(self.num_wmasks):
|
||||
base = vector(i * self.wmask_en_len, 0)
|
||||
self.and2_insts[i].place(base)
|
||||
|
||||
|
||||
def add_layout_pins(self):
|
||||
self.nand2 = factory.create(module_type="pnand2")
|
||||
supply_pin=self.nand2.get_pin("vdd")
|
||||
for i in range(self.num_wmasks):
|
||||
wmask_in_pin = self.and2_insts[i].get_pin("A")
|
||||
self.add_layout_pin(text="wmask_in_{0}".format(i),
|
||||
layer=wmask_in_pin.layer,
|
||||
offset=wmask_in_pin.ll(),
|
||||
width=wmask_in_pin.width(),
|
||||
height=wmask_in_pin.height())
|
||||
self.add_via_center(layers=("metal1", "via1", "metal2"),
|
||||
offset=wmask_in_pin.center())
|
||||
|
||||
en_pin = self.and2_insts[i].get_pin("B")
|
||||
# Add the M1->M2 stack
|
||||
self.add_via_center(layers=("metal1", "via1", "metal2"),
|
||||
offset=en_pin.center())
|
||||
# Add the M2->M3 stack
|
||||
self.add_via_center(layers=("metal2", "via2", "metal3"),
|
||||
offset=en_pin.center())
|
||||
|
||||
# Route en pin between AND gates
|
||||
if i < self.num_wmasks-1:
|
||||
self.add_layout_pin(text="en",
|
||||
layer="metal3",
|
||||
offset=en_pin.bc(),
|
||||
width = self.en_width(i),
|
||||
height = drc('minwidth_metal3'))
|
||||
|
||||
wmask_out_pin = self.and2_insts[i].get_pin("Z")
|
||||
self.add_layout_pin(text="wmask_out_{0}".format(i),
|
||||
layer=wmask_out_pin.layer,
|
||||
offset=wmask_out_pin.ll(),
|
||||
width=wmask_out_pin.width(),
|
||||
height=wmask_out_pin.height())
|
||||
|
||||
self.add_power_pin("gnd", vector(supply_pin.width() + i * self.wmask_en_len, 0))
|
||||
self.add_power_pin("vdd", vector(supply_pin.width() + i * self.wmask_en_len, self.height))
|
||||
|
||||
if i < self.num_wmasks-1:
|
||||
for n in ["gnd","vdd"]:
|
||||
pin = self.and2_insts[i].get_pin(n)
|
||||
next_pin = self.and2_insts[i+1].get_pin(n)
|
||||
self.add_path("metal1",[pin.center(),next_pin.center()])
|
||||
|
||||
|
||||
def en_width(self, pin):
|
||||
en_pin = self.and2_insts[pin].get_pin("B")
|
||||
next_en_pin = self.and2_insts[pin+1].get_pin("B")
|
||||
width = next_en_pin.center() - en_pin.center()
|
||||
# Return x coordinates only
|
||||
return width[0]
|
||||
|
||||
|
||||
def get_cin(self):
|
||||
"""Get the relative capacitance of all the input connections in the bank"""
|
||||
# The enable is connected to an and2 for every row.
|
||||
return self.and2.get_cin() * len(self.and2_insts)
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user