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OpenRAM
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Route RBL to edge of bank.

This commit is contained in:
mrg 2020-03-06 09:03:52 -08:00
parent 05f9e809b4
commit ee18f61cbf
3 changed files with 69 additions and 18 deletions
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31
compiler/modules/bank.py
View File

@ -126,11 +126,22 @@ class bank(design.design):
bl_pin_name = self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port]) bl_pin_name = self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port])
bl_pin = self.bitcell_array_inst.get_pin(bl_pin_name) bl_pin = self.bitcell_array_inst.get_pin(bl_pin_name)
self.add_layout_pin(text="rbl_bl{0}".format(port), # This will ensure the pin is only on the top or bottom edge
layer=bl_pin.layer, if port % 2:
offset=bl_pin.ll(), via_offset = bl_pin.uc()
height=bl_pin.height(), left_right_offset = vector(self.max_x_offset, via_offset.y)
width=bl_pin.width()) else:
via_offset = bl_pin.bc()
left_right_offset = vector(self.min_x_offset, via_offset.y)
if bl_pin == "m1":
self.add_via_center(layers=self.m1_stack,
offset=via_offset)
self.add_via_center(layers=self.m2_stack,
offset=via_offset)
self.add_layout_pin_segment_center(text="rbl_bl{0}".format(port),
layer="m3",
start=left_right_offset,
end=via_offset)
def route_bitlines(self, port): def route_bitlines(self, port):
""" Route the bitlines depending on the port type rw, w, or r. """ """ Route the bitlines depending on the port type rw, w, or r. """
@ -662,9 +673,13 @@ class bank(design.design):
inst2_bl_name = inst2.mod.get_bl_names() + "_{}" inst2_bl_name = inst2.mod.get_bl_names() + "_{}"
inst2_br_name = inst2.mod.get_br_names() + "_{}" inst2_br_name = inst2.mod.get_br_names() + "_{}"
self.connect_bitlines(inst1=inst1, inst2=inst2, num_bits=self.num_cols, self.connect_bitlines(inst1=inst1,
inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name, inst2=inst2,
inst2_bl_name=inst2_bl_name, inst2_br_name=inst2_br_name) num_bits=self.num_cols,
inst1_bl_name=inst1_bl_name,
inst1_br_name=inst1_br_name,
inst2_bl_name=inst2_bl_name,
inst2_br_name=inst2_br_name)
# Connect the replica bitlines # Connect the replica bitlines
rbl_bl_name=self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port]) rbl_bl_name=self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port])

3
compiler/sram/sram_1bank.py
View File

@ -310,7 +310,8 @@ class sram_1bank(sram_base):
# Only input (besides pins) is the replica bitline # Only input (besides pins) is the replica bitline
src_pin = self.control_logic_insts[port].get_pin("rbl_bl") src_pin = self.control_logic_insts[port].get_pin("rbl_bl")
dest_pin = self.bank_inst.get_pin("rbl_bl{}".format(port)) dest_pin = self.bank_inst.get_pin("rbl_bl{}".format(port))
self.connect_vbus_m2m3(src_pin, dest_pin)
self.connect_hbus_m2m3(src_pin, dest_pin)
def route_row_addr_dff(self): def route_row_addr_dff(self):
""" Connect the output of the row flops to the bank pins """ """ Connect the output of the row flops to the bank pins """

51
compiler/sram/sram_base.py
View File

@ -84,7 +84,7 @@ class sram_base(design, verilog, lef):
def create_netlist(self): def create_netlist(self):
""" Netlist creation """ """ Netlist creation """
start_time = datetime.now() start_time = datetime.datetime.now()
# Must create the control logic before pins to get the pins # Must create the control logic before pins to get the pins
self.add_modules() self.add_modules()
@ -96,20 +96,20 @@ class sram_base(design, verilog, lef):
self.height=0 self.height=0
if not OPTS.is_unit_test: if not OPTS.is_unit_test:
print_time("Submodules", datetime.now(), start_time) print_time("Submodules", datetime.datetime.now(), start_time)
def create_layout(self): def create_layout(self):
""" Layout creation """ """ Layout creation """
start_time = datetime.now() start_time = datetime.datetime.now()
self.place_instances() self.place_instances()
if not OPTS.is_unit_test: if not OPTS.is_unit_test:
print_time("Placement", datetime.now(), start_time) print_time("Placement", datetime.datetime.now(), start_time)
start_time = datetime.now() start_time = datetime.datetime.now()
self.route_layout() self.route_layout()
self.route_supplies() self.route_supplies()
if not OPTS.is_unit_test: if not OPTS.is_unit_test:
print_time("Routing", datetime.now(), start_time) print_time("Routing", datetime.datetime.now(), start_time)
self.add_lvs_correspondence_points() self.add_lvs_correspondence_points()
@ -119,11 +119,11 @@ class sram_base(design, verilog, lef):
self.width = highest_coord[0] self.width = highest_coord[0]
self.height = highest_coord[1] self.height = highest_coord[1]
start_time = datetime.now() start_time = datetime.datetime.now()
# We only enable final verification if we have routed the design # We only enable final verification if we have routed the design
self.DRC_LVS(final_verification=OPTS.route_supplies, top_level=True) self.DRC_LVS(final_verification=OPTS.route_supplies, top_level=True)
if not OPTS.is_unit_test: if not OPTS.is_unit_test:
print_time("Verification", datetime.now(), start_time) print_time("Verification", datetime.datetime.now(), start_time)
def create_modules(self): def create_modules(self):
debug.error("Must override pure virtual function.", -1) debug.error("Must override pure virtual function.", -1)
@ -526,6 +526,41 @@ class sram_base(design, verilog, lef):
self.add_via_center(layers=self.m2_stack, self.add_via_center(layers=self.m2_stack,
offset=in_pos) offset=in_pos)
def connect_hbus_m2m3(self, src_pin, dest_pin):
"""
Helper routine to connect an instance to a horizontal bus.
Routes horizontal then vertical L shape.
Dest pin is on M1/M2/M3.
Src pin can be on M1/M2/M3.
"""
if src_pin.cx()<dest_pin.cx():
in_pos = src_pin.rc()
else:
in_pos = src_pin.lc()
if src_pin.cy() < dest_pin.cy():
out_pos = dest_pin.lc()
else:
out_pos = dest_pin.rc()
# move horizontal first
self.add_wire(("m3", "via2", "m2"),
[in_pos,
vector(out_pos.x, in_pos.y),
out_pos])
if src_pin.layer=="m1":
self.add_via_center(layers=self.m1_stack,
offset=in_pos)
if src_pin.layer in ["m1", "m2"]:
self.add_via_center(layers=self.m2_stack,
offset=in_pos)
if dest_pin.layer=="m1":
self.add_via_center(layers=self.m1_stack,
offset=out_pos)
if dest_pin.layer=="m3":
self.add_via_center(layers=self.m2_stack,
offset=out_pos)
def sp_write(self, sp_name): def sp_write(self, sp_name):
# Write the entire spice of the object to the file # Write the entire spice of the object to the file
############################################################ ############################################################