diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py index 60c84a1e..7ba33230 100644 --- a/compiler/modules/bank.py +++ b/compiler/modules/bank.py @@ -126,11 +126,22 @@ class bank(design.design): bl_pin_name = self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port]) bl_pin = self.bitcell_array_inst.get_pin(bl_pin_name) - self.add_layout_pin(text="rbl_bl{0}".format(port), - layer=bl_pin.layer, - offset=bl_pin.ll(), - height=bl_pin.height(), - width=bl_pin.width()) + # This will ensure the pin is only on the top or bottom edge + if port % 2: + via_offset = bl_pin.uc() + left_right_offset = vector(self.max_x_offset, via_offset.y) + else: + via_offset = bl_pin.bc() + left_right_offset = vector(self.min_x_offset, via_offset.y) + if bl_pin == "m1": + self.add_via_center(layers=self.m1_stack, + offset=via_offset) + self.add_via_center(layers=self.m2_stack, + offset=via_offset) + self.add_layout_pin_segment_center(text="rbl_bl{0}".format(port), + layer="m3", + start=left_right_offset, + end=via_offset) def route_bitlines(self, port): """ Route the bitlines depending on the port type rw, w, or r. """ @@ -662,9 +673,13 @@ class bank(design.design): inst2_bl_name = inst2.mod.get_bl_names() + "_{}" inst2_br_name = inst2.mod.get_br_names() + "_{}" - self.connect_bitlines(inst1=inst1, inst2=inst2, num_bits=self.num_cols, - inst1_bl_name=inst1_bl_name, inst1_br_name=inst1_br_name, - inst2_bl_name=inst2_bl_name, inst2_br_name=inst2_br_name) + self.connect_bitlines(inst1=inst1, + inst2=inst2, + num_bits=self.num_cols, + inst1_bl_name=inst1_bl_name, + inst1_br_name=inst1_br_name, + inst2_bl_name=inst2_bl_name, + inst2_br_name=inst2_br_name) # Connect the replica bitlines rbl_bl_name=self.bitcell_array.get_rbl_bl_name(self.port_rbl_map[port]) diff --git a/compiler/sram/sram_1bank.py b/compiler/sram/sram_1bank.py index ae16b6bd..76e9f805 100644 --- a/compiler/sram/sram_1bank.py +++ b/compiler/sram/sram_1bank.py @@ -310,8 +310,9 @@ class sram_1bank(sram_base): # Only input (besides pins) is the replica bitline src_pin = self.control_logic_insts[port].get_pin("rbl_bl") dest_pin = self.bank_inst.get_pin("rbl_bl{}".format(port)) - self.connect_vbus_m2m3(src_pin, dest_pin) - + + self.connect_hbus_m2m3(src_pin, dest_pin) + def route_row_addr_dff(self): """ Connect the output of the row flops to the bank pins """ for port in self.all_ports: diff --git a/compiler/sram/sram_base.py b/compiler/sram/sram_base.py index d2fbe9fc..e8a91486 100644 --- a/compiler/sram/sram_base.py +++ b/compiler/sram/sram_base.py @@ -84,7 +84,7 @@ class sram_base(design, verilog, lef): def create_netlist(self): """ Netlist creation """ - start_time = datetime.now() + start_time = datetime.datetime.now() # Must create the control logic before pins to get the pins self.add_modules() @@ -96,20 +96,20 @@ class sram_base(design, verilog, lef): self.height=0 if not OPTS.is_unit_test: - print_time("Submodules", datetime.now(), start_time) + print_time("Submodules", datetime.datetime.now(), start_time) def create_layout(self): """ Layout creation """ - start_time = datetime.now() + start_time = datetime.datetime.now() self.place_instances() if not OPTS.is_unit_test: - print_time("Placement", datetime.now(), start_time) + print_time("Placement", datetime.datetime.now(), start_time) - start_time = datetime.now() + start_time = datetime.datetime.now() self.route_layout() self.route_supplies() if not OPTS.is_unit_test: - print_time("Routing", datetime.now(), start_time) + print_time("Routing", datetime.datetime.now(), start_time) self.add_lvs_correspondence_points() @@ -119,11 +119,11 @@ class sram_base(design, verilog, lef): self.width = highest_coord[0] self.height = highest_coord[1] - start_time = datetime.now() + start_time = datetime.datetime.now() # We only enable final verification if we have routed the design self.DRC_LVS(final_verification=OPTS.route_supplies, top_level=True) if not OPTS.is_unit_test: - print_time("Verification", datetime.now(), start_time) + print_time("Verification", datetime.datetime.now(), start_time) def create_modules(self): debug.error("Must override pure virtual function.", -1) @@ -526,6 +526,41 @@ class sram_base(design, verilog, lef): self.add_via_center(layers=self.m2_stack, offset=in_pos) + def connect_hbus_m2m3(self, src_pin, dest_pin): + """ + Helper routine to connect an instance to a horizontal bus. + Routes horizontal then vertical L shape. + Dest pin is on M1/M2/M3. + Src pin can be on M1/M2/M3. + """ + + if src_pin.cx()