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add custom module file, make dff clk pin dynamic

This commit is contained in:
jcirimel 2020-02-04 23:35:06 -08:00
parent 6cf20a0353
commit ed11145ca4
3 changed files with 15 additions and 10 deletions
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8
compiler/modules/custom_module_properties.py
View File

@ -7,10 +7,11 @@
# #
class _dff: class _dff:
def __init__(self, use_custom_ports, custom_port_list, custom_type_list): def __init__(self, use_custom_ports, custom_port_list, custom_type_list, clk_pin):
self.use_custom_ports = use_custom_ports self.use_custom_ports = use_custom_ports
self.custom_port_list = custom_port_list self.custom_port_list = custom_port_list
self.custom_type_list = custom_type_list self.custom_type_list = custom_type_list
self.clk_pin = clk_pin
class module_properties(): class module_properties():
""" """
@ -19,8 +20,9 @@ class module_properties():
def __init__(self): def __init__(self):
self.names = {} self.names = {}
self._dff = _dff(use_custom_ports = False, self._dff = _dff(use_custom_ports = False,
custom_port_list = [], custom_port_list = ["D", "Q", "clk", "vdd", "gnd"],
custom_type_list = []) custom_type_list = ["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"],
clk_pin= "clk")
@property @property
def dff(self): def dff(self):

2
compiler/modules/dff.py
View File

@ -18,9 +18,11 @@ class dff(design.design):
if not module_properties.dff.use_custom_ports: if not module_properties.dff.use_custom_ports:
pin_names = ["D", "Q", "clk", "vdd", "gnd"] pin_names = ["D", "Q", "clk", "vdd", "gnd"]
type_list = ["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] type_list = ["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
clk_pin = "clk"
else: else:
pin_names = module_properties.dff.custom_port_list pin_names = module_properties.dff.custom_port_list
type_list = module_properties.dff.custom_type_list type_list = module_properties.dff.custom_type_list
clk_pin = module_properties.dff.clk_pin
(width, height) = utils.get_libcell_size("dff", (width, height) = utils.get_libcell_size("dff",
GDS["unit"], GDS["unit"],

15
compiler/modules/dff_array.py
View File

@ -69,11 +69,12 @@ class dff_array(design.design):
name = "dff_r{0}_c{1}".format(row,col) name = "dff_r{0}_c{1}".format(row,col)
self.dff_insts[row,col]=self.add_inst(name=name, self.dff_insts[row,col]=self.add_inst(name=name,
mod=self.dff) mod=self.dff)
self.connect_inst([self.get_din_name(row,col), instance_ports = [self.get_din_name(row,col),
self.get_dout_name(row,col), self.get_dout_name(row,col)]
"clk", for port in self.dff.pin_names:
"vdd", if port != 'D' and port != 'Q':
"gnd"]) instance_ports.append(port)
self.connect_inst(instance_ports)
def place_dff_array(self): def place_dff_array(self):
for row in range(self.rows): for row in range(self.rows):
@ -142,7 +143,7 @@ class dff_array(design.design):
# Create vertical spines to a single horizontal rail # Create vertical spines to a single horizontal rail
clk_pin = self.dff_insts[0,0].get_pin("clk") clk_pin = self.dff_insts[0,0].get_pin(self.dff.clk_pin)
clk_ypos = 2*self.m3_pitch+self.m3_width clk_ypos = 2*self.m3_pitch+self.m3_width
debug.check(clk_pin.layer=="m2","DFF clk pin not on metal2") debug.check(clk_pin.layer=="m2","DFF clk pin not on metal2")
self.add_layout_pin_segment_center(text="clk", self.add_layout_pin_segment_center(text="clk",
@ -150,7 +151,7 @@ class dff_array(design.design):
start=vector(0,clk_ypos), start=vector(0,clk_ypos),
end=vector(self.width,clk_ypos)) end=vector(self.width,clk_ypos))
for col in range(self.columns): for col in range(self.columns):
clk_pin = self.dff_insts[0,col].get_pin("clk") clk_pin = self.dff_insts[0,col].get_pin(self.dff.clk_pin)
# Make a vertical strip for each column # Make a vertical strip for each column
self.add_rect(layer="m2", self.add_rect(layer="m2",
offset=clk_pin.ll().scale(1,0), offset=clk_pin.ll().scale(1,0),