altered bitcell, pbitcell, and bitcell array modules to accomodate additional bitline reference functions

compiler/modules/bitcell.py

@@ -62,11 +62,21 @@ class bitcell(design.design):
         return row_pins
     
     
-    def list_column_pins(self):
+    def list_all_column_pins(self):
         """ Creates a list of all column pins (except for gnd and vdd) """
         column_pins = ["bl", "br"]
         return column_pins
     
+    def list_column_pins(self):
+        """ Creates a list of all column pins (except for gnd and vdd) """
+        column_pins = ["bl"]
+        return column_pins
+        
+    def list_column_bar_pins(self):
+        """ Creates a list of all column pins (except for gnd and vdd) """
+        column_pins = ["br"]
+        return column_pins
+        
     def list_read_column_pins(self):
         """ Creates a list of column pins associated with read ports """
         column_pins = ["bl"]

compiler/modules/bitcell_array.py

@@ -43,7 +43,7 @@ class bitcell_array(design.design):
 
     def add_pins(self):
         row_list = self.cell.list_row_pins()
-        column_list = self.cell.list_column_pins()
+        column_list = self.cell.list_all_column_pins()
         for col in range(self.column_size):
             for cell_column in column_list:
                 self.add_pin(cell_column+"[{0}]".format(col))
@@ -81,7 +81,9 @@ class bitcell_array(design.design):
     def add_layout_pins(self):
         """ Add the layout pins """
         
-        column_list = self.cell.list_column_pins()
+        row_list = self.cell.list_row_pins()
+        column_list = self.cell.list_all_column_pins()
+        
         offset = vector(0.0, 0.0)
         for col in range(self.column_size):
             for cell_column in column_list:
@@ -95,7 +97,6 @@ class bitcell_array(design.design):
             # increments to the next column width
             offset.x += self.cell.width
 
-        row_list = self.cell.list_row_pins()
         offset.x = 0.0
         for row in range(self.row_size):
             for cell_row in row_list:

compiler/pgates/pbitcell.py

@@ -1090,8 +1090,8 @@ class pbitcell(pgate.pgate):
         return row_pins
     
     
-    def list_column_pins(self):
+    def list_all_column_pins(self):
-        """ Creates a list of all column pins """
+        """ Creates a list of all bitline pins """
         column_pins = []
         for k in range(self.num_readwrite):
             column_pins.append("rwbl{0}".format(k))
@@ -1105,6 +1105,30 @@ class pbitcell(pgate.pgate):
             
         return column_pins
         
+    def list_column_pins(self):
+        """ Creates a list of all bitline bar pins """
+        column_pins = []
+        for k in range(self.num_readwrite):
+            column_pins.append("rwbl{0}".format(k))
+        for k in range(self.num_write):
+            column_pins.append("wbl{0}".format(k))
+        for k in range(self.num_read):
+            column_pins.append("rbl{0}".format(k))
+            
+        return column_pins
+        
+    def list_column_bar_pins(self):
+        """ Creates a list of all bitline bar pins """
+        column_pins = []
+        for k in range(self.num_readwrite):
+            column_pins.append("rwbl_bar{0}".format(k))
+        for k in range(self.num_write):
+            column_pins.append("wbl_bar{0}".format(k))
+        for k in range(self.num_read):
+            column_pins.append("rbl_bar{0}".format(k))
+            
+        return column_pins
+        
     def list_read_column_pins(self):
         """ Creates a list of column pins associated with read ports """
         column_pins = []

compiler/tests/05_pbitcell_array_test.py

@@ -29,21 +29,19 @@ class pbitcell_array_test(openram_test):
         a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
         self.local_check(a)
             
-        debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell")
+        debug.info(2, "Testing 4x4 array for multiport bitcell, with write ports at the edge of the bit cell")
         OPTS.bitcell = "pbitcell"
         OPTS.rw_ports = 2
         OPTS.r_ports = 0
         OPTS.w_ports = 2
-        
-        debug.info(2, "Testing 4x4 array for multiport bitcell, with write ports at the edge of the bit cell")
         a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
         self.local_check(a)
         
+        debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell")
+        OPTS.bitcell = "pbitcell"
         OPTS.rw_ports = 2
         OPTS.r_ports = 0
         OPTS.w_ports = 0
-        
-        debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell")
         a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
         self.local_check(a)