From ecd461216784f348313ea0fa068c5304a8096064 Mon Sep 17 00:00:00 2001 From: Michael Timothy Grimes Date: Sun, 5 Aug 2018 19:43:59 -0700 Subject: [PATCH] altered bitcell, pbitcell, and bitcell array modules to accomodate additional bitline reference functions --- compiler/modules/bitcell.py | 12 +++++++++- compiler/modules/bitcell_array.py | 9 ++++---- compiler/pgates/pbitcell.py | 28 ++++++++++++++++++++++-- compiler/tests/05_pbitcell_array_test.py | 8 +++---- 4 files changed, 45 insertions(+), 12 deletions(-) diff --git a/compiler/modules/bitcell.py b/compiler/modules/bitcell.py index 33707b81..1a8e853e 100644 --- a/compiler/modules/bitcell.py +++ b/compiler/modules/bitcell.py @@ -62,10 +62,20 @@ class bitcell(design.design): return row_pins - def list_column_pins(self): + def list_all_column_pins(self): """ Creates a list of all column pins (except for gnd and vdd) """ column_pins = ["bl", "br"] return column_pins + + def list_column_pins(self): + """ Creates a list of all column pins (except for gnd and vdd) """ + column_pins = ["bl"] + return column_pins + + def list_column_bar_pins(self): + """ Creates a list of all column pins (except for gnd and vdd) """ + column_pins = ["br"] + return column_pins def list_read_column_pins(self): """ Creates a list of column pins associated with read ports """ diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py index dd0ea711..748d1830 100644 --- a/compiler/modules/bitcell_array.py +++ b/compiler/modules/bitcell_array.py @@ -43,7 +43,7 @@ class bitcell_array(design.design): def add_pins(self): row_list = self.cell.list_row_pins() - column_list = self.cell.list_column_pins() + column_list = self.cell.list_all_column_pins() for col in range(self.column_size): for cell_column in column_list: self.add_pin(cell_column+"[{0}]".format(col)) @@ -80,8 +80,10 @@ class bitcell_array(design.design): def add_layout_pins(self): """ Add the layout pins """ - - column_list = self.cell.list_column_pins() + + row_list = self.cell.list_row_pins() + column_list = self.cell.list_all_column_pins() + offset = vector(0.0, 0.0) for col in range(self.column_size): for cell_column in column_list: @@ -95,7 +97,6 @@ class bitcell_array(design.design): # increments to the next column width offset.x += self.cell.width - row_list = self.cell.list_row_pins() offset.x = 0.0 for row in range(self.row_size): for cell_row in row_list: diff --git a/compiler/pgates/pbitcell.py b/compiler/pgates/pbitcell.py index 14df8dce..d9da2158 100644 --- a/compiler/pgates/pbitcell.py +++ b/compiler/pgates/pbitcell.py @@ -1090,8 +1090,8 @@ class pbitcell(pgate.pgate): return row_pins - def list_column_pins(self): - """ Creates a list of all column pins """ + def list_all_column_pins(self): + """ Creates a list of all bitline pins """ column_pins = [] for k in range(self.num_readwrite): column_pins.append("rwbl{0}".format(k)) @@ -1105,6 +1105,30 @@ class pbitcell(pgate.pgate): return column_pins + def list_column_pins(self): + """ Creates a list of all bitline bar pins """ + column_pins = [] + for k in range(self.num_readwrite): + column_pins.append("rwbl{0}".format(k)) + for k in range(self.num_write): + column_pins.append("wbl{0}".format(k)) + for k in range(self.num_read): + column_pins.append("rbl{0}".format(k)) + + return column_pins + + def list_column_bar_pins(self): + """ Creates a list of all bitline bar pins """ + column_pins = [] + for k in range(self.num_readwrite): + column_pins.append("rwbl_bar{0}".format(k)) + for k in range(self.num_write): + column_pins.append("wbl_bar{0}".format(k)) + for k in range(self.num_read): + column_pins.append("rbl_bar{0}".format(k)) + + return column_pins + def list_read_column_pins(self): """ Creates a list of column pins associated with read ports """ column_pins = [] diff --git a/compiler/tests/05_pbitcell_array_test.py b/compiler/tests/05_pbitcell_array_test.py index d208fbff..e8c16607 100644 --- a/compiler/tests/05_pbitcell_array_test.py +++ b/compiler/tests/05_pbitcell_array_test.py @@ -29,21 +29,19 @@ class pbitcell_array_test(openram_test): a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4) self.local_check(a) - debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell") + debug.info(2, "Testing 4x4 array for multiport bitcell, with write ports at the edge of the bit cell") OPTS.bitcell = "pbitcell" OPTS.rw_ports = 2 OPTS.r_ports = 0 OPTS.w_ports = 2 - - debug.info(2, "Testing 4x4 array for multiport bitcell, with write ports at the edge of the bit cell") a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4) self.local_check(a) + debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell") + OPTS.bitcell = "pbitcell" OPTS.rw_ports = 2 OPTS.r_ports = 0 OPTS.w_ports = 0 - - debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell") a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4) self.local_check(a)