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altered bitcell, pbitcell, and bitcell array modules to accomodate additional bitline reference functions

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Michael Timothy Grimes
2018-08-05 19:43:59 -07:00
parent fb0de710ec
commit ecd4612167
4 changed files with 45 additions and 12 deletions
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compiler/tests/05_pbitcell_array_test.py
+3 -5
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@@ -29,21 +29,19 @@ class pbitcell_array_test(openram_test):
a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
self.local_check(a)
debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell")
debug.info(2, "Testing 4x4 array for multiport bitcell, with write ports at the edge of the bit cell")
OPTS.bitcell = "pbitcell"
OPTS.rw_ports = 2
OPTS.r_ports = 0
OPTS.w_ports = 2
debug.info(2, "Testing 4x4 array for multiport bitcell, with write ports at the edge of the bit cell")
a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
self.local_check(a)
debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell")
OPTS.bitcell = "pbitcell"
OPTS.rw_ports = 2
OPTS.r_ports = 0
OPTS.w_ports = 0
debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell")
a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4)
self.local_check(a)