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altered bitcell, pbitcell, and bitcell array modules to accomodate additional bitline reference functions

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Michael Timothy Grimes
2018-08-05 19:43:59 -07:00
parent fb0de710ec
commit ecd4612167
4 changed files with 45 additions and 12 deletions
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compiler/modules/bitcell_array.py
+5 -4
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@@ -43,7 +43,7 @@ class bitcell_array(design.design):
def add_pins(self):
row_list = self.cell.list_row_pins()
column_list = self.cell.list_column_pins()
column_list = self.cell.list_all_column_pins()
for col in range(self.column_size):
for cell_column in column_list:
self.add_pin(cell_column+"[{0}]".format(col))
@@ -80,8 +80,10 @@ class bitcell_array(design.design):
def add_layout_pins(self):
""" Add the layout pins """
column_list = self.cell.list_column_pins()
row_list = self.cell.list_row_pins()
column_list = self.cell.list_all_column_pins()
offset = vector(0.0, 0.0)
for col in range(self.column_size):
for cell_column in column_list:
@@ -95,7 +97,6 @@ class bitcell_array(design.design):
# increments to the next column width
offset.x += self.cell.width
row_list = self.cell.list_row_pins()
offset.x = 0.0
for row in range(self.row_size):
for cell_row in row_list: