From ec28bc6dfdc02a5ae33b789721cb5ff1830904da Mon Sep 17 00:00:00 2001 From: rlin50 Date: Sun, 22 Feb 2026 22:11:35 -0800 Subject: [PATCH] Fix sky130 1rw LVS mismatch by correcting col_cap pin order --- .../sky130/custom/sky130_bitcell_base_array.py | 9 +++++---- technology/sky130/custom/sky130_col_cap_array.py | 12 ++++++------ 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/technology/sky130/custom/sky130_bitcell_base_array.py b/technology/sky130/custom/sky130_bitcell_base_array.py index 9263f8dd..a26f323e 100644 --- a/technology/sky130/custom/sky130_bitcell_base_array.py +++ b/technology/sky130/custom/sky130_bitcell_base_array.py @@ -100,14 +100,15 @@ class sky130_bitcell_base_array(bitcell_base_array): strap_pins = [] for port in self.all_ports: strap_pins.extend([x for x in self.get_bitline_names(port) if "bl" in x and x.endswith("_{0}".format(col))]) - strap_pins.extend(["vdd", "gnd"]) for port in self.all_ports: strap_pins.extend([x for x in self.get_bitline_names(port) if "br" in x and x.endswith("_{0}".format(col))]) + # col_cap_1port_bitcell port order: + # [bl, br, vdd, gnd, vpb, vnb, gate] + strap_pins.extend(["vdd", "gnd", "vdd", "gnd"]) if row == 0: - strap_pins.extend(["top_gate"]) + strap_pins.append("top_gate") else: - strap_pins.extend(["bot_gate"]) - strap_pins.extend(["vdd", "gnd"]) + strap_pins.append("bot_gate") return strap_pins def get_row_cap_pins(self, row, col): diff --git a/technology/sky130/custom/sky130_col_cap_array.py b/technology/sky130/custom/sky130_col_cap_array.py index 445c918c..ded32039 100644 --- a/technology/sky130/custom/sky130_col_cap_array.py +++ b/technology/sky130/custom/sky130_col_cap_array.py @@ -75,12 +75,12 @@ class sky130_col_cap_array(sky130_bitcell_base_array): row_layout.append(self.colend1) self.cell_inst[col]=self.add_inst(name=name, mod=self.colend1) pins.append("fake_bl_{}".format(bitline)) - pins.append("vdd") - pins.append("gnd") pins.append("fake_br_{}".format(bitline)) - pins.append("gate") pins.append("vdd") pins.append("gnd") + pins.append("vdd") + pins.append("gnd") + pins.append("gate") bitline += 1 elif col % 4 == 1: row_layout.append(self.colend2) @@ -92,12 +92,12 @@ class sky130_col_cap_array(sky130_bitcell_base_array): row_layout.append(self.colend1) self.cell_inst[col]=self.add_inst(name=name, mod=self.colend1) pins.append("fake_bl_{}".format(bitline)) - pins.append("vdd") - pins.append("gnd") pins.append("fake_br_{}".format(bitline)) - pins.append("gate") pins.append("vdd") pins.append("gnd") + pins.append("vdd") + pins.append("gnd") + pins.append("gate") bitline += 1 elif col % 4 ==3: row_layout.append(self.colend2)