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https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-02 02:57:53 +02:00
merge local with dev
This commit is contained in:
jcirimel
+17
-9
@@ -15,6 +15,7 @@ from globals import OPTS
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from utils import round_to_grid
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import logical_effort
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from sram_factory import factory
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from errors import drc_error
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class pinv(pgate.pgate):
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@@ -108,11 +109,14 @@ class pinv(pgate.pgate):
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# This is a poly-to-poly of a flipped cell
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self.top_bottom_space = max(0.5*self.m1_width + self.m1_space + extra_contact_space,
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self.poly_extend_active + self.poly_space)
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total_height = tx_height + min_channel + 2 * self.top_bottom_space
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debug.check(self.height > total_height,
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"Cell height {0} too small for simple min height {1}.".format(self.height,
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total_height))
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total_height = tx_height + min_channel + 2 * self.top_bottom_space
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# debug.check(self.height > total_height,
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# "Cell height {0} too small for simple min height {1}.".format(self.height,
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# total_height))
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if total_height > self.height:
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msg = "Cell height {0} too small for simple min height {1}.".format(self.height, total_height)
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raise drc_error(msg)
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# Determine the height left to the transistors to determine
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# the number of fingers
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@@ -144,12 +148,16 @@ class pinv(pgate.pgate):
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# with LVS property mismatch errors when fingers are not a grid
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# length and get rounded in the offset geometry.
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self.nmos_width = round_to_grid(self.nmos_width / self.tx_mults)
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debug.check(self.nmos_width >= drc("minwidth_tx"),
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"Cannot finger NMOS transistors to fit cell height.")
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self.pmos_width = round_to_grid(self.pmos_width / self.tx_mults)
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debug.check(self.pmos_width >= drc("minwidth_tx"),
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"Cannot finger PMOS transistors to fit cell height.")
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# debug.check(self.nmos_width >= drc("minwidth_tx"),
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# "Cannot finger NMOS transistors to fit cell height.")
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if self.nmos_width < drc("minwidth_tx"):
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raise drc_error("Cannot finger NMOS transistors to fit cell height.")
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self.pmos_width = round_to_grid(self.pmos_width / self.tx_mults)
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#debug.check(self.pmos_width >= drc("minwidth_tx"),
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# "Cannot finger PMOS transistors to fit cell height.")
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if self.pmos_width < drc("minwidth_tx"):
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raise drc_error("Cannot finger NMOS transistors to fit cell height.")
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def add_ptx(self):
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""" Create the PMOS and NMOS transistors. """
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+43
-23
@@ -98,7 +98,7 @@ class pnand2(pgate.pgate):
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# metal spacing to allow contacts on any layer
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self.input_spacing = max(self.poly_space + contact.poly_contact.first_layer_width,
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self.m1_space + contact.m1_via.first_layer_width,
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self.m2_space + contact.m2_via.first_layer_width,
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self.m2_space + contact.m2_via.first_layer_width,
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self.m3_space + contact.m2_via.second_layer_width)
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@@ -173,13 +173,15 @@ class pnand2(pgate.pgate):
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0.5 * (pmos1_pos.y + nmos1_pos.y + self.nmos_nd.active_height))
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def add_well_contacts(self):
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"""
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"""
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Add n/p well taps to the layout and connect to supplies
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AFTER the wells are created
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"""
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self.add_nwell_contact(self.pmos, self.pmos2_pos)
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self.add_pwell_contact(self.nmos_nd, self.nmos2_pos)
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self.add_nwell_contact(self.pmos,
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self.pmos2_pos + vector(self.m1_pitch, 0))
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self.add_pwell_contact(self.nmos_nd,
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self.nmos2_pos + vector(self.m1_pitch, 0))
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def connect_rails(self):
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""" Connect the nmos and pmos to its respective power rails """
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@@ -197,7 +199,7 @@ class pnand2(pgate.pgate):
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self.nmos2_inst,
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inputB_yoffset,
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"B",
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position="right")
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position="center")
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# This will help with the wells and the input/output placement
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self.inputA_yoffset = self.pmos2_inst.by() - self.poly_extend_active \
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@@ -209,6 +211,7 @@ class pnand2(pgate.pgate):
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def route_output(self):
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""" Route the Z output """
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# PMOS1 drain
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pmos_pin = self.pmos1_inst.get_pin("D")
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top_pin_offset = pmos_pin.center()
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@@ -217,29 +220,46 @@ class pnand2(pgate.pgate):
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bottom_pin_offset = nmos_pin.center()
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# Output pin
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out_offset = vector(nmos_pin.center().x + self.m1_pitch,
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c_pin = self.get_pin("B")
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out_offset = vector(c_pin.cx() + self.m1_pitch,
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self.inputA_yoffset)
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# Midpoints of the L routes go horizontal first then vertical
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mid1_offset = vector(out_offset.x, top_pin_offset.y)
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# This routes on M2
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# # Midpoints of the L routes go horizontal first then vertical
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# mid1_offset = vector(out_offset.x, top_pin_offset.y)
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# mid2_offset = vector(out_offset.x, bottom_pin_offset.y)
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# # Non-preferred active contacts
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# self.add_via_center(layers=self.m1_stack,
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# directions=("V", "H"),
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# offset=pmos_pin.center())
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# # Non-preferred active contacts
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# self.add_via_center(layers=self.m1_stack,
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# directions=("V", "H"),
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# offset=nmos_pin.center())
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# self.add_via_center(layers=self.m1_stack,
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# offset=out_offset)
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# # PMOS1 to mid-drain to NMOS2 drain
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# self.add_path("m2",
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# [top_pin_offset, mid1_offset, out_offset,
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# mid2_offset, bottom_pin_offset])
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# This routes on M1
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# Midpoints of the L routes goes vertical first then horizontal
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mid1_offset = vector(top_pin_offset.x, out_offset.y)
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# Midpoints of the L routes goes horizontal first then vertical
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mid2_offset = vector(out_offset.x, bottom_pin_offset.y)
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# Non-preferred active contacts
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self.add_via_center(layers=self.m1_stack,
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directions=("V", "H"),
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offset=pmos_pin.center())
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# Non-preferred active contacts
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self.add_via_center(layers=self.m1_stack,
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directions=("V", "H"),
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offset=nmos_pin.center())
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self.add_via_center(layers=self.m1_stack,
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offset=out_offset)
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self.add_path("m1",
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[top_pin_offset, mid1_offset, out_offset])
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# Route in two segments to have the width rule
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self.add_path("m1",
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[bottom_pin_offset, mid2_offset + vector(0.5 * self.m1_width, 0)],
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width=nmos_pin.height())
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self.add_path("m1",
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[mid2_offset, out_offset])
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# PMOS1 to mid-drain to NMOS2 drain
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self.add_path("m2",
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[top_pin_offset, mid1_offset, out_offset,
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mid2_offset, bottom_pin_offset])
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# This extends the output to the edge of the cell
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self.add_layout_pin_rect_center(text="Z",
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layer="m1",
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+57
-23
@@ -12,6 +12,7 @@ from tech import drc, parameter, spice
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from vector import vector
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import logical_effort
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from sram_factory import factory
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from globals import OPTS
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class pnand3(pgate.pgate):
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@@ -190,8 +191,10 @@ class pnand3(pgate.pgate):
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def add_well_contacts(self):
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""" Add n/p well taps to the layout and connect to supplies """
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self.add_nwell_contact(self.pmos, self.pmos3_pos)
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self.add_pwell_contact(self.nmos_ns, self.nmos3_pos)
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self.add_nwell_contact(self.pmos,
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self.pmos3_pos + vector(self.m1_pitch, 0))
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self.add_pwell_contact(self.nmos_ns,
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self.nmos3_pos + vector(self.m1_pitch, 0))
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def connect_rails(self):
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""" Connect the nmos and pmos to its respective power rails """
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@@ -220,18 +223,22 @@ class pnand3(pgate.pgate):
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self.nmos3_inst,
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self.inputC_yoffset,
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"C",
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position="center")
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position="right")
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# FIXME: constant hack
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self.inputA_yoffset = self.inputB_yoffset + 1.12 * m1_pitch
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if OPTS.tech_name == "s8":
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self.inputA_yoffset = self.inputB_yoffset + 1.15 * m1_pitch
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else:
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self.inputA_yoffset = self.inputB_yoffset + 1.12 * m1_pitch
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self.route_input_gate(self.pmos1_inst,
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self.nmos1_inst,
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self.inputA_yoffset,
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"A",
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position="center")
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position="left")
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def route_output(self):
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""" Route the Z output """
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# PMOS1 drain
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pmos1_pin = self.pmos1_inst.get_pin("D")
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# PMOS3 drain
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@@ -239,29 +246,56 @@ class pnand3(pgate.pgate):
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# NMOS3 drain
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nmos3_pin = self.nmos3_inst.get_pin("D")
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# Go up to metal2 for ease on all output pins
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self.add_via_center(layers=self.m1_stack,
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offset=pmos1_pin.center(),
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directions=("V", "V"))
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self.add_via_center(layers=self.m1_stack,
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offset=pmos3_pin.center(),
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directions=("V", "V"))
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self.add_via_center(layers=self.m1_stack,
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offset=nmos3_pin.center(),
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directions=("V", "V"))
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# midpoint for routing
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mid_offset = vector(nmos3_pin.cx() + self.m1_pitch,
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self.inputA_yoffset)
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# Aligned with the well taps
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out_offset = vector(self.nwell_contact.cx(),
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self.inputA_yoffset)
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# PMOS3 and NMOS3 are drain aligned
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self.add_path("m2", [pmos3_pin.center(), nmos3_pin.center()])
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# Route in the A input track (top track)
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mid_offset = vector(nmos3_pin.center().x, self.inputA_yoffset)
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self.add_path("m2", [pmos1_pin.center(), mid_offset, nmos3_pin.uc()])
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# Go up to metal2 for ease on all output pins
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# self.add_via_center(layers=self.m1_stack,
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# offset=pmos1_pin.center(),
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# directions=("V", "V"))
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# self.add_via_center(layers=self.m1_stack,
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# offset=pmos3_pin.center(),
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# directions=("V", "V"))
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# self.add_via_center(layers=self.m1_stack,
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# offset=nmos3_pin.center(),
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# directions=("V", "V"))
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# # Route in the A input track (top track)
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# mid_offset = vector(nmos3_pin.center().x, self.inputA_yoffset)
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# self.add_path("m1", [pmos1_pin.center(), mid_offset, nmos3_pin.uc()])
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# This extends the output to the edge of the cell
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self.add_via_center(layers=self.m1_stack,
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offset=mid_offset)
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# self.add_via_center(layers=self.m1_stack,
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# offset=mid_offset)
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top_left_pin_offset = pmos1_pin.center()
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top_right_pin_offset = pmos3_pin.center()
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bottom_pin_offset = nmos3_pin.center()
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# PMOS1 to output
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self.add_path("m1", [top_left_pin_offset,
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vector(top_left_pin_offset.x, out_offset.y),
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out_offset])
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# PMOS3 to output
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self.add_path("m1", [top_right_pin_offset,
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vector(top_right_pin_offset.x, mid_offset.y),
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mid_offset])
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# NMOS3 to output
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mid2_offset = vector(mid_offset.x, bottom_pin_offset.y)
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self.add_path("m1",
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[bottom_pin_offset, mid2_offset],
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width=nmos3_pin.height())
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mid3_offset = vector(mid_offset.x, nmos3_pin.by())
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self.add_path("m1", [mid3_offset, mid_offset])
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self.add_layout_pin_rect_center(text="Z",
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layer="m1",
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offset=mid_offset,
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offset=out_offset,
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width=contact.m1_via.first_layer_width,
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height=contact.m1_via.first_layer_height)
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+25
-17
@@ -107,10 +107,7 @@ class ptx(design.design):
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# be decided in the layout later.
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area_sd = 2.5 * self.poly_width * self.tx_width
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perimeter_sd = 2 * self.poly_width + 2 * self.tx_width
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if OPTS.tech_name == None:
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print("here {0}".format(self.name))
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if OPTS.tech_name == "s8":
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# s8 technology is in microns
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main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type],
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self.mults,
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@@ -474,13 +471,13 @@ class ptx(design.design):
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"""Returns an object representing the parameters for delay in tau units."""
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# FIXME: Using the same definition as the pinv.py.
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parasitic_delay = 1
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size = self.mults*self.tx_width/drc("minwidth_tx")
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return logical_effort.logical_effort(self.name,
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size,
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self.input_load(),
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cout,
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parasitic_delay)
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parasitic_delay = 1
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size = self.mults * self.tx_width / drc("minwidth_tx")
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return logical_effort.logical_effort(self.name,
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size,
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self.input_load(),
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cout,
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parasitic_delay)
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def input_load(self):
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"""
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@@ -488,7 +485,7 @@ class ptx(design.design):
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"""
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# FIXME: this will be applied for the loads of the drain/source
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return self.mults*self.tx_width/drc("minwidth_tx")
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return self.mults * self.tx_width / drc("minwidth_tx")
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def add_diff_contact(self, label, pos):
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contact=self.add_via_center(layers=self.active_stack,
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@@ -499,14 +496,25 @@ class ptx(design.design):
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well_type=self.well_type)
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if hasattr(self, "li_stack"):
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self.add_via_center(layers=self.li_stack,
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offset=pos)
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contact=self.add_via_center(layers=self.li_stack,
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offset=pos,
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directions=("V", "V"))
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# contact_area = contact.mod.second_layer_width * contact.mod.second_layer_height
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# min_area = drc("minarea_m1")
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# width = contact.mod.second_layer_width
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# if contact_area < min_area:
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# height = min_area / width
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# else:
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# height = contact.mod.second_layer_height
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width = contact.mod.second_layer_width
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height = contact.mod.second_layer_height
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self.add_layout_pin_rect_center(text=label,
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layer="m1",
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offset=pos,
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width=contact.mod.second_layer_width,
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height=contact.mod.second_layer_height)
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width=width,
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height=height)
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return(contact)
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def get_cin(self):
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