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Connect all gnd rails of RBL.

This commit is contained in:
Matt Guthaus 2018-02-02 12:27:24 -08:00
parent d552d88f45
commit ea5eda91fc
1 changed files with 13 additions and 18 deletions
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31
compiler/replica_bitline.py
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@ -242,16 +242,11 @@ class replica_bitline(design.design):
# Add a rail in M1 from bottom to two along delay chain
gnd_start = self.rbl_inv_inst.get_pin("gnd").ll() - self.offset_fix
# It is the height of the entire RBL and bitcell
self.add_rect(layer="metal2",
offset=gnd_start,
width=self.m2_width,
height=self.rbl.height+self.bitcell.height+self.inv.width+self.m2_pitch)
self.add_layout_pin(text="gnd",
layer="metal1",
layer="metal2",
offset=gnd_start.scale(1,0),
width=self.m2_width,
height=2*self.inv.width)
height=self.rbl_inst.uy()+2*self.m2_pitch)
# Connect the WL pins directly to gnd
for row in range(self.rows):
@ -275,20 +270,20 @@ class replica_bitline(design.design):
self.add_via(layers=("metal1", "via1", "metal2"),
offset=offset)
# Connect the bitcell gnd pin to the rail
# Connect the bitcell gnd pins to the rail
gnd_pins = self.get_pins("gnd")
gnd_start = gnd_pins[0].uc()
gnd_start = gnd_pins[0].ul()
self.add_via_center(layers=("metal1", "via1", "metal2"),
offset=gnd_pins[0].uc())
rbl_gnd_pins = self.rbl_inst.get_pins("gnd")
# Find the left most rail on M2
gnd_pin = None
# Add L shapes to each vertical gnd rail
for pin in rbl_gnd_pins:
if gnd_pin == None or (pin.layer=="metal2" and pin.lx()<gnd_pin.lx()):
gnd_pin = pin
gnd_end = gnd_pin.uc()
# Add a couple midpoints so that the wire will drop a via and then route horizontal on M1
gnd_mid1 = gnd_start + vector(0,self.m2_pitch)
gnd_mid2 = gnd_end + vector(0,self.m2_pitch)
self.add_wire(("metal1","via1","metal2"), [gnd_start, gnd_mid1, gnd_mid2, gnd_end])
if pin.layer != "metal2":
continue
gnd_end = pin.uc()
gnd_mid = vector(gnd_end.x, gnd_start.y)
self.add_wire(("metal1","via1","metal2"), [gnd_start, gnd_mid, gnd_end])
gnd_start = gnd_mid
# Add a second gnd pin to the second delay chain rail. No need for full length.