From ea5eda91fcacdcb211d106abf51d885da33a392c Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 2 Feb 2018 12:27:24 -0800 Subject: [PATCH] Connect all gnd rails of RBL. --- compiler/replica_bitline.py | 31 +++++++++++++------------------ 1 file changed, 13 insertions(+), 18 deletions(-) diff --git a/compiler/replica_bitline.py b/compiler/replica_bitline.py index bed1ebb2..9345cb48 100644 --- a/compiler/replica_bitline.py +++ b/compiler/replica_bitline.py @@ -242,16 +242,11 @@ class replica_bitline(design.design): # Add a rail in M1 from bottom to two along delay chain gnd_start = self.rbl_inv_inst.get_pin("gnd").ll() - self.offset_fix - # It is the height of the entire RBL and bitcell - self.add_rect(layer="metal2", - offset=gnd_start, - width=self.m2_width, - height=self.rbl.height+self.bitcell.height+self.inv.width+self.m2_pitch) self.add_layout_pin(text="gnd", - layer="metal1", + layer="metal2", offset=gnd_start.scale(1,0), width=self.m2_width, - height=2*self.inv.width) + height=self.rbl_inst.uy()+2*self.m2_pitch) # Connect the WL pins directly to gnd for row in range(self.rows): @@ -275,20 +270,20 @@ class replica_bitline(design.design): self.add_via(layers=("metal1", "via1", "metal2"), offset=offset) - # Connect the bitcell gnd pin to the rail + # Connect the bitcell gnd pins to the rail gnd_pins = self.get_pins("gnd") - gnd_start = gnd_pins[0].uc() + gnd_start = gnd_pins[0].ul() + self.add_via_center(layers=("metal1", "via1", "metal2"), + offset=gnd_pins[0].uc()) rbl_gnd_pins = self.rbl_inst.get_pins("gnd") - # Find the left most rail on M2 - gnd_pin = None + # Add L shapes to each vertical gnd rail for pin in rbl_gnd_pins: - if gnd_pin == None or (pin.layer=="metal2" and pin.lx()