mirror of https://github.com/VLSIDA/OpenRAM.git
Connect all gnd rails of RBL.
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@ -242,16 +242,11 @@ class replica_bitline(design.design):
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# Add a rail in M1 from bottom to two along delay chain
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# Add a rail in M1 from bottom to two along delay chain
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gnd_start = self.rbl_inv_inst.get_pin("gnd").ll() - self.offset_fix
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gnd_start = self.rbl_inv_inst.get_pin("gnd").ll() - self.offset_fix
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# It is the height of the entire RBL and bitcell
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self.add_rect(layer="metal2",
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offset=gnd_start,
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width=self.m2_width,
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height=self.rbl.height+self.bitcell.height+self.inv.width+self.m2_pitch)
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self.add_layout_pin(text="gnd",
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self.add_layout_pin(text="gnd",
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layer="metal1",
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layer="metal2",
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offset=gnd_start.scale(1,0),
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offset=gnd_start.scale(1,0),
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width=self.m2_width,
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width=self.m2_width,
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height=2*self.inv.width)
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height=self.rbl_inst.uy()+2*self.m2_pitch)
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# Connect the WL pins directly to gnd
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# Connect the WL pins directly to gnd
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for row in range(self.rows):
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for row in range(self.rows):
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@ -275,20 +270,20 @@ class replica_bitline(design.design):
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self.add_via(layers=("metal1", "via1", "metal2"),
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self.add_via(layers=("metal1", "via1", "metal2"),
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offset=offset)
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offset=offset)
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# Connect the bitcell gnd pin to the rail
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# Connect the bitcell gnd pins to the rail
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gnd_pins = self.get_pins("gnd")
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gnd_pins = self.get_pins("gnd")
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gnd_start = gnd_pins[0].uc()
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gnd_start = gnd_pins[0].ul()
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=gnd_pins[0].uc())
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rbl_gnd_pins = self.rbl_inst.get_pins("gnd")
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rbl_gnd_pins = self.rbl_inst.get_pins("gnd")
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# Find the left most rail on M2
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# Add L shapes to each vertical gnd rail
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gnd_pin = None
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for pin in rbl_gnd_pins:
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for pin in rbl_gnd_pins:
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if gnd_pin == None or (pin.layer=="metal2" and pin.lx()<gnd_pin.lx()):
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if pin.layer != "metal2":
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gnd_pin = pin
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continue
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gnd_end = gnd_pin.uc()
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gnd_end = pin.uc()
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# Add a couple midpoints so that the wire will drop a via and then route horizontal on M1
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gnd_mid = vector(gnd_end.x, gnd_start.y)
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gnd_mid1 = gnd_start + vector(0,self.m2_pitch)
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self.add_wire(("metal1","via1","metal2"), [gnd_start, gnd_mid, gnd_end])
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gnd_mid2 = gnd_end + vector(0,self.m2_pitch)
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gnd_start = gnd_mid
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self.add_wire(("metal1","via1","metal2"), [gnd_start, gnd_mid1, gnd_mid2, gnd_end])
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# Add a second gnd pin to the second delay chain rail. No need for full length.
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# Add a second gnd pin to the second delay chain rail. No need for full length.
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