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Changed s_en delay calculation based recent control logic changes.

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Hunter Nichols
2018-12-05 17:10:11 -08:00
parent 0c3c58011b
commit ea55bda493
10 changed files with 66 additions and 79 deletions
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compiler/tests/22_psram_1bank_2mux_func_test.py
+1 -1
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@@ -11,7 +11,7 @@ import globals
from globals import OPTS
import debug
@unittest.skip("SKIPPING 22_psram_1bank_2mux_1rw_1r_1w_func_test, third port reads are broken?")
#@unittest.skip("SKIPPING 22_psram_1bank_2mux_1rw_1r_1w_func_test, third port reads are broken?")
class psram_1bank_2mux_1rw_1r_1w_func_test(openram_test):
def runTest(self):
compiler/tests/22_psram_1bank_4mux_func_test.py
+1 -1
View File
@@ -11,7 +11,7 @@ import globals
from globals import OPTS
import debug
@unittest.skip("SKIPPING 22_psram_1bank_4mux_func_test, third port reads are broken?")
#@unittest.skip("SKIPPING 22_psram_1bank_4mux_func_test, third port reads are broken?")
class psram_1bank_4mux_func_test(openram_test):
def runTest(self):