mirror of https://github.com/VLSIDA/OpenRAM.git
PEP8 cleanup
This commit is contained in:
mrg
parent
1564d6e02b
commit
e95c97d7a5
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@ -5,18 +5,16 @@
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from math import log
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import design
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from tech import drc, parameter
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from tech import cell_properties as props
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import debug
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import contact
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from sram_factory import factory
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import math
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from vector import vector
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from globals import OPTS
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import logical_effort
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class control_logic(design.design):
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"""
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Dynamically generated Control logic for the total SRAM circuit.
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@ -44,6 +42,7 @@ class control_logic(design.design):
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self.inv_parasitic_delay = logical_effort.logical_effort.pinv
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# Determines how much larger the sen delay should be. Accounts for possible error in model.
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# FIXME: This should be made a parameter
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self.wl_timing_tolerance = 1
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self.wl_stage_efforts = None
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self.sen_stage_efforts = None
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@ -71,7 +70,6 @@ class control_logic(design.design):
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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""" Add the pins to the control logic module. """
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self.add_pin_list(self.input_list + ["clk"] + self.rbl_list, "INPUT")
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@ -101,7 +99,6 @@ class control_logic(design.design):
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height=dff_height)
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self.add_mod(self.rbl_driver)
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# clk_buf drives a flop for every address
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addr_flops = math.log(self.num_words, 2) + math.log(self.words_per_row, 2)
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# plus data flops and control flops
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@ -151,7 +148,6 @@ class control_logic(design.design):
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height=dff_height)
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self.add_mod(self.p_en_bar_driver)
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self.nand2 = factory.create(module_type="pnand2",
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height=dff_height)
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self.add_mod(self.nand2)
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@ -195,7 +191,8 @@ class control_logic(design.design):
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# self.sen_delay_rise,self.sen_delay_fall = self.get_delays_to_sen() #get the new timing
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# self.delay_chain_resized = True
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debug.check(OPTS.delay_chain_stages%2, "Must use odd number of delay chain stages for inverting delay chain.")
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debug.check(OPTS.delay_chain_stages % 2,
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"Must use odd number of delay chain stages for inverting delay chain.")
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self.delay_chain=factory.create(module_type="delay_chain",
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fanout_list = OPTS.delay_chain_stages * [ OPTS.delay_chain_fanout_per_stage ])
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self.add_mod(self.delay_chain)
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@ -251,13 +248,16 @@ class control_logic(design.design):
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previous_delay_chain_delay = (previous_fanout + 1 + self.inv_parasitic_delay) * previous_stages
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debug.info(2, "Previous delay chain produced {} delay units".format(previous_delay_chain_delay))
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delay_fanout = 3 # This can be anything >=2
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# This can be anything >=2
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delay_fanout = 3
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# The delay chain uses minimum sized inverters. There are (fanout+1)*stages inverters and each
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# inverter adds 1 unit of delay (due to minimum size). This also depends on the pinv value
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required_delay = self.wl_delay * self.wl_timing_tolerance - (self.sen_delay - previous_delay_chain_delay)
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debug.check(required_delay > 0, "Cannot size delay chain to have negative delay")
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delay_stages = ceil(required_delay/(delay_fanout+1+self.inv_parasitic_delay))
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if delay_stages%2 == 1: #force an even number of stages.
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delay_per_stage = delay_fanout + 1 + self.inv_parasitic_delay
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delay_stages = ceil(required_delay / delay_per_stage)
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# force an even number of stages.
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if delay_stages % 2 == 1:
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delay_stages += 1
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# Fanout can be varied as well but is a little more complicated but potentially optimal.
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debug.info(1, "Setting delay chain to {} stages with {} fanout to match {} delay".format(delay_stages, delay_fanout, required_delay))
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@ -266,24 +266,33 @@ class control_logic(design.design):
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def get_dynamic_delay_fanout_list(self, previous_stages, previous_fanout):
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"""Determine the size of the delay chain used for the Sense Amp Enable using path delays"""
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previous_delay_chain_delay = (previous_fanout+1+self.inv_parasitic_delay)*previous_stages
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previous_delay_per_stage = previous_fanout + 1 + self.inv_parasitic_delay
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previous_delay_chain_delay = previous_delay_per_stage * previous_stages
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debug.info(2, "Previous delay chain produced {} delay units".format(previous_delay_chain_delay))
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fanout_rise = fanout_fall = 2 # This can be anything >=2
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# The delay chain uses minimum sized inverters. There are (fanout+1)*stages inverters and each
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# inverter adds 1 unit of delay (due to minimum size). This also depends on the pinv value
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required_delay_fall = self.wl_delay_fall*self.wl_timing_tolerance - (self.sen_delay_fall-previous_delay_chain_delay/2)
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required_delay_rise = self.wl_delay_rise*self.wl_timing_tolerance - (self.sen_delay_rise-previous_delay_chain_delay/2)
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debug.info(2,"Required delays from chain: fall={}, rise={}".format(required_delay_fall,required_delay_rise))
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required_delay_fall = self.wl_delay_fall * self.wl_timing_tolerance - \
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(self.sen_delay_fall - previous_delay_chain_delay / 2)
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required_delay_rise = self.wl_delay_rise * self.wl_timing_tolerance - \
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(self.sen_delay_rise - previous_delay_chain_delay / 2)
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debug.info(2,
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"Required delays from chain: fall={}, rise={}".format(required_delay_fall,
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required_delay_rise))
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# If the fanout is different between rise/fall by this amount. Stage algorithm is made more pessimistic.
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WARNING_FANOUT_DIFF = 5
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stages_close = False
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# The stages need to be equal (or at least a even number of stages with matching rise/fall delays)
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while True:
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stages_fall = self.calculate_stages_with_fixed_fanout(required_delay_fall,fanout_fall)
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stages_rise = self.calculate_stages_with_fixed_fanout(required_delay_rise,fanout_rise)
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debug.info(1,"Fall stages={}, rise stages={}".format(stages_fall,stages_rise))
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stages_fall = self.calculate_stages_with_fixed_fanout(required_delay_fall,
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fanout_fall)
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stages_rise = self.calculate_stages_with_fixed_fanout(required_delay_rise,
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fanout_rise)
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debug.info(1,
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"Fall stages={}, rise stages={}".format(stages_fall,
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stages_rise))
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if abs(stages_fall - stages_rise) == 1 and not stages_close:
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stages_close = True
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safe_fanout_rise = fanout_rise
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@ -313,13 +322,17 @@ class control_logic(design.design):
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def calculate_stages_with_fixed_fanout(self, required_delay, fanout):
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from math import ceil
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# Delay being negative is not an error. It implies that any amount of stages would have a negative effect on the overall delay
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if required_delay <= 3+self.inv_parasitic_delay: #3 is the minimum delay per stage (with pinv=0).
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# 3 is the minimum delay per stage (with pinv=0).
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if required_delay <= 3 + self.inv_parasitic_delay:
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return 1
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delay_stages = ceil(required_delay/(fanout+1+self.inv_parasitic_delay))
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delay_per_stage = fanout + 1 + self.inv_parasitic_delay
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delay_stages = ceil(required_delay / delay_per_stage)
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return delay_stages
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def calculate_stage_list(self, total_stages, fanout_rise, fanout_fall):
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"""Produces a list of fanouts which determine the size of the delay chain. List length is the number of stages.
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"""
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Produces a list of fanouts which determine the size of the delay chain.
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List length is the number of stages.
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Assumes the first stage is falling.
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"""
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stage_list = []
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@ -366,7 +379,6 @@ class control_logic(design.design):
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self.supply_list = ["vdd", "gnd"]
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def route_rails(self):
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""" Add the input signal inverted tracks """
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height = self.control_logic_center.y - self.m2_pitch
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@ -374,7 +386,6 @@ class control_logic(design.design):
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self.rail_offsets = self.create_vertical_bus("m2", self.m2_pitch, offset, self.internal_bus_list, height)
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def create_instances(self):
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""" Create all the instances """
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self.create_dffs()
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@ -390,8 +401,6 @@ class control_logic(design.design):
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self.create_delay()
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self.create_pen_row()
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def place_instances(self):
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""" Place all the instances """
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# Keep track of all right-most instances to determine row boundary
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@ -459,7 +468,6 @@ class control_logic(design.design):
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self.route_gated_clk_buf()
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self.route_supply()
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def create_delay(self):
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""" Create the replica bitline """
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self.delay_inst=self.add_inst(name="delay_chain",
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@ -488,11 +496,9 @@ class control_logic(design.design):
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self.add_via_center(layers=self.m1_stack,
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offset=in_pos)
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# Input from RBL goes to the delay line for futher delay
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self.copy_layout_pin(self.delay_inst, "in", "rbl_bl")
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def create_clk_buf_row(self):
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""" Create the multistage and gated clock buffer """
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self.clk_buf_inst = self.add_inst(name="clkbuf",
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@ -516,13 +522,12 @@ class control_logic(design.design):
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self.add_via_center(layers=self.m1_stack,
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offset=clk_pos)
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# Connect this at the bottom of the buffer
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out_pos = self.clk_buf_inst.get_pin("Z").center()
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mid1 = vector(out_pos.x, 2 * self.m2_pitch)
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mid2 = vector(self.rail_offsets["clk_buf"].x, mid1.y)
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bus_pos = self.rail_offsets["clk_buf"]
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self.add_wire(("m3","via2","m2"),[out_pos, mid1, mid2, bus_pos])
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self.add_wire(self.m2_stack[::-1], [out_pos, mid1, mid2, bus_pos])
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# The pin is on M1, so we need another via as well
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self.add_via_center(layers=self.m1_stack,
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offset=self.clk_buf_inst.get_pin("Z").center())
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@ -557,15 +562,20 @@ class control_logic(design.design):
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# This is the second gate over, so it needs to be on M3
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clkbuf_map = zip(["A"], ["cs"])
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self.connect_vertical_bus(clkbuf_map, self.gated_clk_bar_inst, self.rail_offsets, ("m3", "via2", "m2"))
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self.connect_vertical_bus(clkbuf_map,
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self.gated_clk_bar_inst,
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self.rail_offsets,
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self.m2_stack[::-1])
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# The pin is on M1, so we need another via as well
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self.add_via_center(layers=self.m1_stack,
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offset=self.gated_clk_bar_inst.get_pin("A").center())
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# This is the second gate over, so it needs to be on M3
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clkbuf_map = zip(["Z"], ["gated_clk_bar"])
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self.connect_vertical_bus(clkbuf_map, self.gated_clk_bar_inst, self.rail_offsets, ("m3", "via2", "m2"))
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self.connect_vertical_bus(clkbuf_map,
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self.gated_clk_bar_inst,
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self.rail_offsets,
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self.m2_stack[::-1])
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# The pin is on M1, so we need another via as well
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self.add_via_center(layers=self.m1_stack,
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offset=self.gated_clk_bar_inst.get_pin("Z").center())
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@ -586,9 +596,11 @@ class control_logic(design.design):
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clkbuf_map = zip(["A", "B"], ["clk_buf", "cs"])
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self.connect_vertical_bus(clkbuf_map, self.gated_clk_buf_inst, self.rail_offsets)
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clkbuf_map = zip(["Z"], ["gated_clk_buf"])
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self.connect_vertical_bus(clkbuf_map, self.gated_clk_buf_inst, self.rail_offsets, ("m3", "via2", "m2"))
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self.connect_vertical_bus(clkbuf_map,
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self.gated_clk_buf_inst,
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self.rail_offsets,
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self.m2_stack[::-1])
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# The pin is on M1, so we need another via as well
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self.add_via_center(layers=self.m1_stack,
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offset=self.gated_clk_buf_inst.get_pin("Z").center())
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@ -656,7 +668,6 @@ class control_logic(design.design):
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# hence we use rbl_bl_delay as well.
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self.connect_inst(["rbl_bl_delay", "gated_clk_bar", input_name, "s_en", "vdd", "gnd"])
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def place_sen_row(self, row):
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x_offset = self.control_x_offset
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@ -664,7 +675,6 @@ class control_logic(design.design):
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self.row_end_inst.append(self.s_en_gate_inst)
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def route_sen(self):
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if self.port_type=="rw":
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@ -700,11 +710,9 @@ class control_logic(design.design):
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self.add_via_center(layers=self.m1_stack,
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offset=self.rbl_bl_delay_inv_inst.get_pin("Z").center())
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rbl_map = zip(["A"], ["rbl_bl_delay"])
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self.connect_vertical_bus(rbl_map, self.rbl_bl_delay_inv_inst, self.rail_offsets)
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def create_wen_row(self):
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# input: we (or cs) output: w_en
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@ -720,7 +728,6 @@ class control_logic(design.design):
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# Only drive the writes in the second half of the clock cycle during a write operation.
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self.connect_inst([input_name, "rbl_bl_delay_bar", "gated_clk_bar", "w_en", "vdd", "gnd"])
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def place_wen_row(self, row):
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x_offset = self.control_x_offset
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@ -784,7 +791,6 @@ class control_logic(design.design):
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return (y_off, mirror)
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def connect_output(self, inst, pin_name, out_name):
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""" Create an output pin on the right side from the pin of a given instance. """
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@ -795,8 +801,6 @@ class control_logic(design.design):
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start=out_pin.center(),
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end=right_pos)
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def route_supply(self):
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""" Add vdd and gnd to the instance cells """
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@ -824,8 +828,6 @@ class control_logic(design.design):
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self.copy_layout_pin(self.ctrl_dff_inst, "gnd")
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self.copy_layout_pin(self.ctrl_dff_inst, "vdd")
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def add_lvs_correspondence_points(self):
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""" This adds some points for easier debugging if LVS goes wrong.
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These should probably be turned off by default though, since extraction
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@ -852,17 +854,18 @@ class control_logic(design.design):
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height=pin.height(),
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width=pin.width())
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def get_delays_to_wl(self):
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"""Get the delay (in delay units) of the clk to a wordline in the bitcell array"""
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debug.check(self.sram.all_mods_except_control_done, "Cannot calculate sense amp enable delay unless all module have been added.")
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self.wl_stage_efforts = self.get_wordline_stage_efforts()
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clk_to_wl_rise, clk_to_wl_fall = logical_effort.calculate_relative_rise_fall_delays(self.wl_stage_efforts)
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total_delay = clk_to_wl_rise + clk_to_wl_fall
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debug.info(1, "Clock to wl delay is rise={:.3f}, fall={:.3f}, total={:.3f} in delay units".format(clk_to_wl_rise, clk_to_wl_fall,total_delay))
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debug.info(1,
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"Clock to wl delay is rise={:.3f}, fall={:.3f}, total={:.3f} in delay units".format(clk_to_wl_rise,
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clk_to_wl_fall,
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total_delay))
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return clk_to_wl_rise, clk_to_wl_fall
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def get_wordline_stage_efforts(self):
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"""Follows the gated_clk_bar -> wl_en -> wordline signal for the total path efforts"""
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stage_effort_list = []
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@ -882,14 +885,18 @@ class control_logic(design.design):
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return stage_effort_list
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def get_delays_to_sen(self):
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"""Get the delay (in delay units) of the clk to a sense amp enable.
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"""
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Get the delay (in delay units) of the clk to a sense amp enable.
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This does not incorporate the delay of the replica bitline.
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"""
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debug.check(self.sram.all_mods_except_control_done, "Cannot calculate sense amp enable delay unless all module have been added.")
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self.sen_stage_efforts = self.get_sa_enable_stage_efforts()
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clk_to_sen_rise, clk_to_sen_fall = logical_effort.calculate_relative_rise_fall_delays(self.sen_stage_efforts)
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total_delay = clk_to_sen_rise + clk_to_sen_fall
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debug.info(1, "Clock to s_en delay is rise={:.3f}, fall={:.3f}, total={:.3f} in delay units".format(clk_to_sen_rise, clk_to_sen_fall,total_delay))
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debug.info(1,
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"Clock to s_en delay is rise={:.3f}, fall={:.3f}, total={:.3f} in delay units".format(clk_to_sen_rise,
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clk_to_sen_fall,
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total_delay))
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return clk_to_sen_rise, clk_to_sen_fall
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def get_sa_enable_stage_efforts(self):
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@ -931,7 +938,7 @@ class control_logic(design.design):
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stage_effort_list = []
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# Calculate the load on clk_buf_bar
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ext_clk_buf_cout = self.sram.get_clk_bar_cin()
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# ext_clk_buf_cout = self.sram.get_clk_bar_cin()
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# Operations logic starts on negative edge
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last_stage_rise = False
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