mirror of https://github.com/VLSIDA/OpenRAM.git
Make pinvbuf have unique names for GDS compliance.
Add back gating of w_en since write should happen in second half or else we will have write and precharge simultaneously active.
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@ -349,12 +349,12 @@ class control_logic(design.design):
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# input: WE, CS output: w_en_bar
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# input: WE, CS output: w_en_bar
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w_en_bar_offset = vector(x_off, y_off)
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w_en_bar_offset = vector(x_off, y_off)
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self.w_en_bar_inst=self.add_inst(name="nand2_w_en_bar",
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self.w_en_bar_inst=self.add_inst(name="nand3_w_en_bar",
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mod=self.nand2,
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mod=self.nand3,
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offset=w_en_bar_offset,
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offset=w_en_bar_offset,
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mirror=mirror)
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mirror=mirror)
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self.connect_inst(["cs", "we", "w_en_bar", "vdd", "gnd"])
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self.connect_inst(["clk_buf_bar", "cs", "we", "w_en_bar", "vdd", "gnd"])
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x_off += self.nand2.width
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x_off += self.nand3.width
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# input: w_en_bar, output: pre_w_en
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# input: w_en_bar, output: pre_w_en
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pre_w_en_offset = vector(x_off, y_off)
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pre_w_en_offset = vector(x_off, y_off)
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@ -460,7 +460,7 @@ class control_logic(design.design):
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def route_wen(self):
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def route_wen(self):
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wen_map = zip(["A", "B"], ["cs", "we"])
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wen_map = zip(["A", "B", "C"], ["clk_buf_bar", "cs", "we"])
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self.connect_vertical_bus(wen_map, self.w_en_bar_inst, self.rail_offsets)
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self.connect_vertical_bus(wen_map, self.w_en_bar_inst, self.rail_offsets)
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# Connect the NAND3 output to the inverter
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# Connect the NAND3 output to the inverter
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@ -15,6 +15,8 @@ class pinvbuf(design.design):
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c = reload(__import__(OPTS.bitcell))
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c = reload(__import__(OPTS.bitcell))
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bitcell = getattr(c, OPTS.bitcell)
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bitcell = getattr(c, OPTS.bitcell)
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unique_id = 1
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def __init__(self, driver_size=4, height=bitcell.height, name=""):
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def __init__(self, driver_size=4, height=bitcell.height, name=""):
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stage_effort = 4
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stage_effort = 4
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@ -26,7 +28,9 @@ class pinvbuf(design.design):
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predriver_size = max(int(driver_size/(stage_effort/2)),1)
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predriver_size = max(int(driver_size/(stage_effort/2)),1)
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if name=="":
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if name=="":
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name = "pinvbuf_{0}_{1}".format(predriver_size, driver_size)
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name = "pinvbuf_{0}_{1}_{2}".format(predriver_size, driver_size, pinvbuf.unique_id)
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pinvbuf.unique_id += 1
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design.design.__init__(self, name)
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design.design.__init__(self, name)
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debug.info(1, "Creating {}".format(self.name))
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debug.info(1, "Creating {}".format(self.name))
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