From e827c1b8c747a8cede3f0317fa111b45ab69cab0 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Thu, 26 Jul 2018 11:40:40 -0700 Subject: [PATCH] Make pinvbuf have unique names for GDS compliance. Add back gating of w_en since write should happen in second half or else we will have write and precharge simultaneously active. --- compiler/modules/control_logic.py | 10 +++++----- compiler/pgates/pinvbuf.py | 6 +++++- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index 570434ee..99018a9a 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -349,12 +349,12 @@ class control_logic(design.design): # input: WE, CS output: w_en_bar w_en_bar_offset = vector(x_off, y_off) - self.w_en_bar_inst=self.add_inst(name="nand2_w_en_bar", - mod=self.nand2, + self.w_en_bar_inst=self.add_inst(name="nand3_w_en_bar", + mod=self.nand3, offset=w_en_bar_offset, mirror=mirror) - self.connect_inst(["cs", "we", "w_en_bar", "vdd", "gnd"]) - x_off += self.nand2.width + self.connect_inst(["clk_buf_bar", "cs", "we", "w_en_bar", "vdd", "gnd"]) + x_off += self.nand3.width # input: w_en_bar, output: pre_w_en pre_w_en_offset = vector(x_off, y_off) @@ -460,7 +460,7 @@ class control_logic(design.design): def route_wen(self): - wen_map = zip(["A", "B"], ["cs", "we"]) + wen_map = zip(["A", "B", "C"], ["clk_buf_bar", "cs", "we"]) self.connect_vertical_bus(wen_map, self.w_en_bar_inst, self.rail_offsets) # Connect the NAND3 output to the inverter diff --git a/compiler/pgates/pinvbuf.py b/compiler/pgates/pinvbuf.py index 3f483e05..6347c157 100644 --- a/compiler/pgates/pinvbuf.py +++ b/compiler/pgates/pinvbuf.py @@ -15,6 +15,8 @@ class pinvbuf(design.design): c = reload(__import__(OPTS.bitcell)) bitcell = getattr(c, OPTS.bitcell) + unique_id = 1 + def __init__(self, driver_size=4, height=bitcell.height, name=""): stage_effort = 4 @@ -26,7 +28,9 @@ class pinvbuf(design.design): predriver_size = max(int(driver_size/(stage_effort/2)),1) if name=="": - name = "pinvbuf_{0}_{1}".format(predriver_size, driver_size) + name = "pinvbuf_{0}_{1}_{2}".format(predriver_size, driver_size, pinvbuf.unique_id) + pinvbuf.unique_id += 1 + design.design.__init__(self, name) debug.info(1, "Creating {}".format(self.name))