diff --git a/compiler/globals.py b/compiler/globals.py
index 01c52725..0865d581 100644
--- a/compiler/globals.py
+++ b/compiler/globals.py
@@ -185,7 +185,7 @@ def check_versions():
         OPTS.coverage = 0
 
 
-def init_openram(config_file, is_unit_test=True):
+def init_openram(config_file, is_unit_test=False):
     """ Initialize the technology, paths, simulators, etc. """
 
     check_versions()
@@ -294,7 +294,7 @@ def get_tool(tool_type, preferences, default_name=None):
             return(None, "")
 
 
-def read_config(config_file, is_unit_test=True):
+def read_config(config_file, is_unit_test=False):
     """
     Read the configuration file that defines a few parameters. The
     config file is just a Python file that defines some config
diff --git a/compiler/tests/01_library_test.py b/compiler/tests/01_library_test.py
index 03a7f1f3..9a6b5702 100755
--- a/compiler/tests/01_library_test.py
+++ b/compiler/tests/01_library_test.py
@@ -18,7 +18,7 @@ class library_lvs_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         import verify
 
         (gds_dir, sp_dir, allnames) = setup_files()
diff --git a/compiler/tests/03_contact_test.py b/compiler/tests/03_contact_test.py
index 34c96063..251d517e 100755
--- a/compiler/tests/03_contact_test.py
+++ b/compiler/tests/03_contact_test.py
@@ -19,7 +19,7 @@ class contact_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         from tech import active_stack, poly_stack, beol_stacks
 
diff --git a/compiler/tests/03_path_test.py b/compiler/tests/03_path_test.py
index a08edad7..e2f46b90 100755
--- a/compiler/tests/03_path_test.py
+++ b/compiler/tests/03_path_test.py
@@ -18,7 +18,7 @@ class path_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from base import wire_path
         import tech
         from base import design
diff --git a/compiler/tests/03_ptx_1finger_nmos_test.py b/compiler/tests/03_ptx_1finger_nmos_test.py
index 2ebf7d45..d7281c87 100755
--- a/compiler/tests/03_ptx_1finger_nmos_test.py
+++ b/compiler/tests/03_ptx_1finger_nmos_test.py
@@ -20,7 +20,7 @@ class ptx_1finger_nmos_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         import tech
 
         debug.info(2, "Checking min size NMOS with 1 finger")
diff --git a/compiler/tests/03_ptx_1finger_pmos_test.py b/compiler/tests/03_ptx_1finger_pmos_test.py
index 53922c9b..85c4088a 100755
--- a/compiler/tests/03_ptx_1finger_pmos_test.py
+++ b/compiler/tests/03_ptx_1finger_pmos_test.py
@@ -19,7 +19,7 @@ class ptx_1finger_pmos_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         import tech
 
         debug.info(2, "Checking min size PMOS with 1 finger")
diff --git a/compiler/tests/03_ptx_3finger_nmos_test.py b/compiler/tests/03_ptx_3finger_nmos_test.py
index a4e18aa2..5bc43a14 100755
--- a/compiler/tests/03_ptx_3finger_nmos_test.py
+++ b/compiler/tests/03_ptx_3finger_nmos_test.py
@@ -19,7 +19,7 @@ class ptx_3finger_nmos_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         import tech
 
         debug.info(2, "Checking three fingers NMOS")
diff --git a/compiler/tests/03_ptx_3finger_pmos_test.py b/compiler/tests/03_ptx_3finger_pmos_test.py
index b4776456..699a5190 100755
--- a/compiler/tests/03_ptx_3finger_pmos_test.py
+++ b/compiler/tests/03_ptx_3finger_pmos_test.py
@@ -19,7 +19,7 @@ class ptx_3finger_pmos_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         import tech
 
         debug.info(2, "Checking three fingers PMOS")
diff --git a/compiler/tests/03_ptx_4finger_nmos_test.py b/compiler/tests/03_ptx_4finger_nmos_test.py
index c1c2184b..41c05f84 100755
--- a/compiler/tests/03_ptx_4finger_nmos_test.py
+++ b/compiler/tests/03_ptx_4finger_nmos_test.py
@@ -19,7 +19,7 @@ class ptx_4finger_nmos_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         import tech
 
         debug.info(2, "Checking three fingers NMOS")
diff --git a/compiler/tests/03_ptx_4finger_pmos_test.py b/compiler/tests/03_ptx_4finger_pmos_test.py
index fcc843bb..ae2c88e2 100755
--- a/compiler/tests/03_ptx_4finger_pmos_test.py
+++ b/compiler/tests/03_ptx_4finger_pmos_test.py
@@ -19,7 +19,7 @@ class ptx_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         import tech
 
         debug.info(2, "Checking three fingers PMOS")
diff --git a/compiler/tests/03_ptx_no_contacts_test.py b/compiler/tests/03_ptx_no_contacts_test.py
index 36b53d8f..ad6e346c 100755
--- a/compiler/tests/03_ptx_no_contacts_test.py
+++ b/compiler/tests/03_ptx_no_contacts_test.py
@@ -20,7 +20,7 @@ class ptx_no_contacts_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         import tech
 
         debug.info(2, "Checking single finger no source/drain")
diff --git a/compiler/tests/03_wire_test.py b/compiler/tests/03_wire_test.py
index 8906e1cf..5f4b0661 100755
--- a/compiler/tests/03_wire_test.py
+++ b/compiler/tests/03_wire_test.py
@@ -18,7 +18,7 @@ class wire_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from base import wire
         import tech
         from base import design
diff --git a/compiler/tests/04_and2_dec_test.py b/compiler/tests/04_and2_dec_test.py
index 93ad6d41..bae4c274 100755
--- a/compiler/tests/04_and2_dec_test.py
+++ b/compiler/tests/04_and2_dec_test.py
@@ -20,7 +20,7 @@ class and2_dec_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         global verify
         import verify
 
diff --git a/compiler/tests/04_and3_dec_test.py b/compiler/tests/04_and3_dec_test.py
index 6b6389e3..24d5364b 100755
--- a/compiler/tests/04_and3_dec_test.py
+++ b/compiler/tests/04_and3_dec_test.py
@@ -20,7 +20,7 @@ class and3_dec_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         global verify
         import verify
 
diff --git a/compiler/tests/04_and4_dec_test.py b/compiler/tests/04_and4_dec_test.py
index c849e6d6..c860eeca 100755
--- a/compiler/tests/04_and4_dec_test.py
+++ b/compiler/tests/04_and4_dec_test.py
@@ -21,7 +21,7 @@ class and4_dec_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         global verify
         import verify
 
diff --git a/compiler/tests/04_column_mux_1rw_1r_test.py b/compiler/tests/04_column_mux_1rw_1r_test.py
index 56b4301a..61b42f6c 100755
--- a/compiler/tests/04_column_mux_1rw_1r_test.py
+++ b/compiler/tests/04_column_mux_1rw_1r_test.py
@@ -20,7 +20,7 @@ class column_mux_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/04_column_mux_pbitcell_test.py b/compiler/tests/04_column_mux_pbitcell_test.py
index 4ce02164..24ec4129 100755
--- a/compiler/tests/04_column_mux_pbitcell_test.py
+++ b/compiler/tests/04_column_mux_pbitcell_test.py
@@ -20,7 +20,7 @@ class column_mux_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check single level column mux in multi-port
         OPTS.bitcell = "pbitcell"
diff --git a/compiler/tests/04_column_mux_test.py b/compiler/tests/04_column_mux_test.py
index 78770b5b..814c4733 100755
--- a/compiler/tests/04_column_mux_test.py
+++ b/compiler/tests/04_column_mux_test.py
@@ -20,7 +20,7 @@ class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check single level column mux in single port
         debug.info(2, "Checking column mux")
diff --git a/compiler/tests/04_dff_buf_test.py b/compiler/tests/04_dff_buf_test.py
index c8d2842e..7eb6f37a 100755
--- a/compiler/tests/04_dff_buf_test.py
+++ b/compiler/tests/04_dff_buf_test.py
@@ -20,7 +20,7 @@ class dff_buf_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         debug.info(2, "Testing dff_buf 4x 8x")
         a = factory.create(module_type="dff_buf", inv1_size=4, inv2_size=8)
         self.local_check(a)
diff --git a/compiler/tests/04_dummy_pbitcell_test.py b/compiler/tests/04_dummy_pbitcell_test.py
index 0d955283..ef214268 100755
--- a/compiler/tests/04_dummy_pbitcell_test.py
+++ b/compiler/tests/04_dummy_pbitcell_test.py
@@ -19,7 +19,7 @@ class replica_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import dummy_pbitcell
 
         OPTS.bitcell = "pbitcell"
diff --git a/compiler/tests/04_pand2_test.py b/compiler/tests/04_pand2_test.py
index d1e9f6ff..0740c5f6 100755
--- a/compiler/tests/04_pand2_test.py
+++ b/compiler/tests/04_pand2_test.py
@@ -19,7 +19,7 @@ class pand2_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         global verify
         import verify
 
diff --git a/compiler/tests/04_pand3_test.py b/compiler/tests/04_pand3_test.py
index 3b49e3a1..d75ff484 100755
--- a/compiler/tests/04_pand3_test.py
+++ b/compiler/tests/04_pand3_test.py
@@ -19,7 +19,7 @@ class pand3_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         global verify
         import verify
 
diff --git a/compiler/tests/04_pand4_test.py b/compiler/tests/04_pand4_test.py
index 2c5f5878..941a8626 100755
--- a/compiler/tests/04_pand4_test.py
+++ b/compiler/tests/04_pand4_test.py
@@ -19,7 +19,7 @@ class pand4_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         global verify
         import verify
 
diff --git a/compiler/tests/04_pbitcell_test.py b/compiler/tests/04_pbitcell_test.py
index 119afc41..227b6755 100755
--- a/compiler/tests/04_pbitcell_test.py
+++ b/compiler/tests/04_pbitcell_test.py
@@ -20,7 +20,7 @@ class pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports=1
         OPTS.num_w_ports=1
diff --git a/compiler/tests/04_pbuf_dec_8x_test.py b/compiler/tests/04_pbuf_dec_8x_test.py
index 823f9bcc..6de1f48c 100755
--- a/compiler/tests/04_pbuf_dec_8x_test.py
+++ b/compiler/tests/04_pbuf_dec_8x_test.py
@@ -19,7 +19,7 @@ class pbuf_dec_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/04_pbuf_test.py b/compiler/tests/04_pbuf_test.py
index 72a5f2ff..83ffcde4 100755
--- a/compiler/tests/04_pbuf_test.py
+++ b/compiler/tests/04_pbuf_test.py
@@ -19,7 +19,7 @@ class pbuf_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing buffer 8x")
         a = factory.create(module_type="pbuf", size=8)
diff --git a/compiler/tests/04_pdriver_test.py b/compiler/tests/04_pdriver_test.py
index 71ad80cd..c2def4ac 100755
--- a/compiler/tests/04_pdriver_test.py
+++ b/compiler/tests/04_pdriver_test.py
@@ -19,7 +19,7 @@ class pdriver_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing inverter/buffer 4x 8x")
         # a tests the error message for specifying conflicting conditions
diff --git a/compiler/tests/04_pinv_100x_test.py b/compiler/tests/04_pinv_100x_test.py
index 0d86e0a8..62fc48b9 100755
--- a/compiler/tests/04_pinv_100x_test.py
+++ b/compiler/tests/04_pinv_100x_test.py
@@ -19,7 +19,7 @@ class pinv_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 100x inverter")
         tx = factory.create(module_type="pinv", size=100)
diff --git a/compiler/tests/04_pinv_10x_test.py b/compiler/tests/04_pinv_10x_test.py
index 8151bf41..81be4e27 100755
--- a/compiler/tests/04_pinv_10x_test.py
+++ b/compiler/tests/04_pinv_10x_test.py
@@ -19,7 +19,7 @@ class pinv_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 8x inverter")
         tx = factory.create(module_type="pinv", size=8)
diff --git a/compiler/tests/04_pinv_1x_beta_test.py b/compiler/tests/04_pinv_1x_beta_test.py
index 9ecbc3aa..6554ee99 100755
--- a/compiler/tests/04_pinv_1x_beta_test.py
+++ b/compiler/tests/04_pinv_1x_beta_test.py
@@ -19,7 +19,7 @@ class pinv_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 1x beta=3 size inverter")
         tx = factory.create(module_type="pinv", size=1, beta=3)
diff --git a/compiler/tests/04_pinv_1x_test.py b/compiler/tests/04_pinv_1x_test.py
index f6f4ca04..26fbbcb8 100755
--- a/compiler/tests/04_pinv_1x_test.py
+++ b/compiler/tests/04_pinv_1x_test.py
@@ -19,7 +19,7 @@ class pinv_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 1x size inverter")
         tx = factory.create(module_type="pinv", size=1)
diff --git a/compiler/tests/04_pinv_2x_test.py b/compiler/tests/04_pinv_2x_test.py
index 0ae30973..e341396f 100755
--- a/compiler/tests/04_pinv_2x_test.py
+++ b/compiler/tests/04_pinv_2x_test.py
@@ -19,7 +19,7 @@ class pinv_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 2x size inverter")
         tx = factory.create(module_type="pinv", size=2)
diff --git a/compiler/tests/04_pinv_dec_1x_test.py b/compiler/tests/04_pinv_dec_1x_test.py
index 7aee5219..b5c4d264 100755
--- a/compiler/tests/04_pinv_dec_1x_test.py
+++ b/compiler/tests/04_pinv_dec_1x_test.py
@@ -20,7 +20,7 @@ class pinv_dec_1x_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/04_pinvbuf_test.py b/compiler/tests/04_pinvbuf_test.py
index 4f227181..a3fc10ae 100755
--- a/compiler/tests/04_pinvbuf_test.py
+++ b/compiler/tests/04_pinvbuf_test.py
@@ -19,7 +19,7 @@ class pinvbuf_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing inverter/buffer 4x 8x")
         a = factory.create(module_type="pinvbuf", size=8)
diff --git a/compiler/tests/04_pnand2_test.py b/compiler/tests/04_pnand2_test.py
index 053e343c..facd2625 100755
--- a/compiler/tests/04_pnand2_test.py
+++ b/compiler/tests/04_pnand2_test.py
@@ -19,7 +19,7 @@ class pnand2_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 2-input nand gate")
         tx = factory.create(module_type="pnand2", size=1)
diff --git a/compiler/tests/04_pnand3_test.py b/compiler/tests/04_pnand3_test.py
index a934f698..e51a837f 100755
--- a/compiler/tests/04_pnand3_test.py
+++ b/compiler/tests/04_pnand3_test.py
@@ -19,7 +19,7 @@ class pnand3_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 3-input nand gate")
         tx = factory.create(module_type="pnand3", size=1)
diff --git a/compiler/tests/04_pnand4_test.py b/compiler/tests/04_pnand4_test.py
index bceff7f9..88449fce 100755
--- a/compiler/tests/04_pnand4_test.py
+++ b/compiler/tests/04_pnand4_test.py
@@ -20,7 +20,7 @@ class pnand4_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 4-input nand gate")
         tx = factory.create(module_type="pnand4", size=1)
diff --git a/compiler/tests/04_pnor2_test.py b/compiler/tests/04_pnor2_test.py
index a68a7190..566b16b8 100755
--- a/compiler/tests/04_pnor2_test.py
+++ b/compiler/tests/04_pnor2_test.py
@@ -19,7 +19,7 @@ class pnor2_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 2-input nor gate")
         tx = factory.create(module_type="pnor2", size=1)
diff --git a/compiler/tests/04_precharge_1rw_1r_test.py b/compiler/tests/04_precharge_1rw_1r_test.py
index 026deaee..3739a9a0 100755
--- a/compiler/tests/04_precharge_1rw_1r_test.py
+++ b/compiler/tests/04_precharge_1rw_1r_test.py
@@ -20,7 +20,7 @@ class precharge_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check precharge array in multi-port
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/04_precharge_pbitcell_test.py b/compiler/tests/04_precharge_pbitcell_test.py
index ae9740fb..32f625ce 100755
--- a/compiler/tests/04_precharge_pbitcell_test.py
+++ b/compiler/tests/04_precharge_pbitcell_test.py
@@ -19,7 +19,7 @@ class precharge_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check precharge in multi-port
         OPTS.bitcell = "pbitcell"
diff --git a/compiler/tests/04_precharge_test.py b/compiler/tests/04_precharge_test.py
index 3d1d3832..5cf57f9a 100755
--- a/compiler/tests/04_precharge_test.py
+++ b/compiler/tests/04_precharge_test.py
@@ -20,7 +20,7 @@ class precharge_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check precharge in single port
         debug.info(2, "Checking precharge for handmade bitcell")
diff --git a/compiler/tests/04_pwrite_driver_test.py b/compiler/tests/04_pwrite_driver_test.py
index 7d2d525b..08adc62f 100755
--- a/compiler/tests/04_pwrite_driver_test.py
+++ b/compiler/tests/04_pwrite_driver_test.py
@@ -20,7 +20,7 @@ import debug
 class pwrite_driver_test(openram_test):
 
     def runTest(self):
-        globals.init_openram("config_{0}".format(OPTS.tech_name))
+        globals.init_openram("config_{0}".format(OPTS.tech_name), is_unit_test=True)
 
         debug.info(2, "Checking 1x pwrite_driver")
         tx = factory.create(module_type="pwrite_driver", size=1)
diff --git a/compiler/tests/04_replica_pbitcell_test.py b/compiler/tests/04_replica_pbitcell_test.py
index 5b4e7271..7249e094 100755
--- a/compiler/tests/04_replica_pbitcell_test.py
+++ b/compiler/tests/04_replica_pbitcell_test.py
@@ -19,7 +19,7 @@ class replica_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import replica_pbitcell
 
         OPTS.bitcell = "pbitcell"
diff --git a/compiler/tests/04_wordline_driver_test.py b/compiler/tests/04_wordline_driver_test.py
index c71e3190..168ac6bc 100755
--- a/compiler/tests/04_wordline_driver_test.py
+++ b/compiler/tests/04_wordline_driver_test.py
@@ -21,7 +21,7 @@ class wordline_driver_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check wordline driver for single port
         debug.info(2, "Checking driver")
diff --git a/compiler/tests/05_bitcell_array_1rw_1r_test.py b/compiler/tests/05_bitcell_array_1rw_1r_test.py
index 3ae9a7d7..da9bb597 100755
--- a/compiler/tests/05_bitcell_array_1rw_1r_test.py
+++ b/compiler/tests/05_bitcell_array_1rw_1r_test.py
@@ -20,7 +20,7 @@ class bitcell_array_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/05_bitcell_array_test.py b/compiler/tests/05_bitcell_array_test.py
index 738a038e..cfa80767 100755
--- a/compiler/tests/05_bitcell_array_test.py
+++ b/compiler/tests/05_bitcell_array_test.py
@@ -20,7 +20,7 @@ class array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing 8x8 array for 6t_cell")
 
diff --git a/compiler/tests/05_dummy_array_test.py b/compiler/tests/05_dummy_array_test.py
index 41eb7b0b..c4730416 100755
--- a/compiler/tests/05_dummy_array_test.py
+++ b/compiler/tests/05_dummy_array_test.py
@@ -17,7 +17,7 @@ class dummy_row_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing dummy row for 6t_cell")
         a = factory.create(module_type="dummy_array", rows=1, cols=4)
diff --git a/compiler/tests/05_pbitcell_array_test.py b/compiler/tests/05_pbitcell_array_test.py
index 8a05dcec..cb90e58f 100755
--- a/compiler/tests/05_pbitcell_array_test.py
+++ b/compiler/tests/05_pbitcell_array_test.py
@@ -20,7 +20,7 @@ class pbitcell_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing 4x4 array for multiport bitcell, with read ports at the edge of the bit cell")
         OPTS.bitcell = "pbitcell"
diff --git a/compiler/tests/06_column_decoder_16row_test.py b/compiler/tests/06_column_decoder_16row_test.py
index d34d6879..9c6b5508 100755
--- a/compiler/tests/06_column_decoder_16row_test.py
+++ b/compiler/tests/06_column_decoder_16row_test.py
@@ -20,7 +20,7 @@ class column_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
diff --git a/compiler/tests/06_hierarchical_decoder_132row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_132row_1rw_1r_test.py
index 26aeb899..c145a6a4 100755
--- a/compiler/tests/06_hierarchical_decoder_132row_1rw_1r_test.py
+++ b/compiler/tests/06_hierarchical_decoder_132row_1rw_1r_test.py
@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/06_hierarchical_decoder_132row_test.py b/compiler/tests/06_hierarchical_decoder_132row_test.py
index d1655a25..77be88dc 100755
--- a/compiler/tests/06_hierarchical_decoder_132row_test.py
+++ b/compiler/tests/06_hierarchical_decoder_132row_test.py
@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
diff --git a/compiler/tests/06_hierarchical_decoder_16row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_16row_1rw_1r_test.py
index aad79dd4..159c5ea5 100755
--- a/compiler/tests/06_hierarchical_decoder_16row_1rw_1r_test.py
+++ b/compiler/tests/06_hierarchical_decoder_16row_1rw_1r_test.py
@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/06_hierarchical_decoder_16row_test.py b/compiler/tests/06_hierarchical_decoder_16row_test.py
index fc379cc4..74b39b95 100755
--- a/compiler/tests/06_hierarchical_decoder_16row_test.py
+++ b/compiler/tests/06_hierarchical_decoder_16row_test.py
@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
diff --git a/compiler/tests/06_hierarchical_decoder_17row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_17row_1rw_1r_test.py
index d81f6774..b100a05e 100755
--- a/compiler/tests/06_hierarchical_decoder_17row_1rw_1r_test.py
+++ b/compiler/tests/06_hierarchical_decoder_17row_1rw_1r_test.py
@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/06_hierarchical_decoder_17row_test.py b/compiler/tests/06_hierarchical_decoder_17row_test.py
index ff7d1662..487f3eb7 100755
--- a/compiler/tests/06_hierarchical_decoder_17row_test.py
+++ b/compiler/tests/06_hierarchical_decoder_17row_test.py
@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
diff --git a/compiler/tests/06_hierarchical_decoder_32row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_32row_1rw_1r_test.py
index 7ec03133..eabf7693 100755
--- a/compiler/tests/06_hierarchical_decoder_32row_1rw_1r_test.py
+++ b/compiler/tests/06_hierarchical_decoder_32row_1rw_1r_test.py
@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/06_hierarchical_decoder_32row_test.py b/compiler/tests/06_hierarchical_decoder_32row_test.py
index 895b63dc..c567f510 100755
--- a/compiler/tests/06_hierarchical_decoder_32row_test.py
+++ b/compiler/tests/06_hierarchical_decoder_32row_test.py
@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
diff --git a/compiler/tests/06_hierarchical_decoder_4096row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_4096row_1rw_1r_test.py
index c0058da4..0db29543 100755
--- a/compiler/tests/06_hierarchical_decoder_4096row_1rw_1r_test.py
+++ b/compiler/tests/06_hierarchical_decoder_4096row_1rw_1r_test.py
@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/06_hierarchical_decoder_4096row_test.py b/compiler/tests/06_hierarchical_decoder_4096row_test.py
index 14e3f113..f8d497cc 100755
--- a/compiler/tests/06_hierarchical_decoder_4096row_test.py
+++ b/compiler/tests/06_hierarchical_decoder_4096row_test.py
@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
diff --git a/compiler/tests/06_hierarchical_decoder_512row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_512row_1rw_1r_test.py
index 5982e930..82592dce 100755
--- a/compiler/tests/06_hierarchical_decoder_512row_1rw_1r_test.py
+++ b/compiler/tests/06_hierarchical_decoder_512row_1rw_1r_test.py
@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/06_hierarchical_decoder_512row_test.py b/compiler/tests/06_hierarchical_decoder_512row_test.py
index 6ad92d86..48ad81ae 100755
--- a/compiler/tests/06_hierarchical_decoder_512row_test.py
+++ b/compiler/tests/06_hierarchical_decoder_512row_test.py
@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
diff --git a/compiler/tests/06_hierarchical_decoder_64row_1rw_1r_test.py b/compiler/tests/06_hierarchical_decoder_64row_1rw_1r_test.py
index 6dd3b4de..52bea3d7 100755
--- a/compiler/tests/06_hierarchical_decoder_64row_1rw_1r_test.py
+++ b/compiler/tests/06_hierarchical_decoder_64row_1rw_1r_test.py
@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/06_hierarchical_decoder_64row_test.py b/compiler/tests/06_hierarchical_decoder_64row_test.py
index 37b97732..aadec410 100755
--- a/compiler/tests/06_hierarchical_decoder_64row_test.py
+++ b/compiler/tests/06_hierarchical_decoder_64row_test.py
@@ -20,7 +20,7 @@ class hierarchical_decoder_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
diff --git a/compiler/tests/06_hierarchical_decoder_pbitcell_test.py b/compiler/tests/06_hierarchical_decoder_pbitcell_test.py
index 2548e498..5dcd6b16 100755
--- a/compiler/tests/06_hierarchical_decoder_pbitcell_test.py
+++ b/compiler/tests/06_hierarchical_decoder_pbitcell_test.py
@@ -20,7 +20,7 @@ class hierarchical_decoder_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         # check hierarchical decoder for multi-port
         OPTS.num_rw_ports = 1
         OPTS.num_w_ports = 0
diff --git a/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py b/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py
index 0cff264a..4940bebe 100755
--- a/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py
+++ b/compiler/tests/06_hierarchical_predecode2x4_1rw_1r_test.py
@@ -20,7 +20,7 @@ class hierarchical_predecode2x4_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py b/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py
index bb9523a9..8f7ef312 100755
--- a/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py
+++ b/compiler/tests/06_hierarchical_predecode2x4_pbitcell_test.py
@@ -20,7 +20,7 @@ class hierarchical_predecode2x4_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # checking hierarchical precode 2x4 for multi-port
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/06_hierarchical_predecode2x4_test.py b/compiler/tests/06_hierarchical_predecode2x4_test.py
index d8680f53..31d14067 100755
--- a/compiler/tests/06_hierarchical_predecode2x4_test.py
+++ b/compiler/tests/06_hierarchical_predecode2x4_test.py
@@ -20,7 +20,7 @@ class hierarchical_predecode2x4_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for hierarchy_predecode2x4")
         a = factory.create(module_type="hierarchical_predecode2x4")
diff --git a/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py b/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py
index d6580991..8d51d862 100755
--- a/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py
+++ b/compiler/tests/06_hierarchical_predecode3x8_1rw_1r_test.py
@@ -20,7 +20,7 @@ class hierarchical_predecode3x8_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # Use the 2 port cell since it is usually bigger/easier
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py b/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py
index 1ddc91df..f01f6ad1 100755
--- a/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py
+++ b/compiler/tests/06_hierarchical_predecode3x8_pbitcell_test.py
@@ -20,7 +20,7 @@ class hierarchical_predecode3x8_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # checking hierarchical precode 3x8 for multi-port
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/06_hierarchical_predecode3x8_test.py b/compiler/tests/06_hierarchical_predecode3x8_test.py
index 3ff4a252..14a498cd 100755
--- a/compiler/tests/06_hierarchical_predecode3x8_test.py
+++ b/compiler/tests/06_hierarchical_predecode3x8_test.py
@@ -20,7 +20,7 @@ class hierarchical_predecode3x8_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for hierarchy_predecode3x8")
         a = factory.create(module_type="hierarchical_predecode3x8")
diff --git a/compiler/tests/06_hierarchical_predecode4x16_test.py b/compiler/tests/06_hierarchical_predecode4x16_test.py
index ff855601..6a4ef9e6 100755
--- a/compiler/tests/06_hierarchical_predecode4x16_test.py
+++ b/compiler/tests/06_hierarchical_predecode4x16_test.py
@@ -20,7 +20,7 @@ class hierarchical_predecode4x16_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # Use the 2 port cell since it is usually bigger/easier
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/07_column_mux_array_16mux_1rw_1r_test.py b/compiler/tests/07_column_mux_array_16mux_1rw_1r_test.py
index 36d086a8..cb5503c7 100755
--- a/compiler/tests/07_column_mux_array_16mux_1rw_1r_test.py
+++ b/compiler/tests/07_column_mux_array_16mux_1rw_1r_test.py
@@ -19,7 +19,7 @@ class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/07_column_mux_array_16mux_test.py b/compiler/tests/07_column_mux_array_16mux_test.py
index 51634eae..b26bc971 100755
--- a/compiler/tests/07_column_mux_array_16mux_test.py
+++ b/compiler/tests/07_column_mux_array_16mux_test.py
@@ -19,7 +19,7 @@ class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for 16-way column_mux_array")
         a = factory.create(module_type="column_mux_array", columns=64, word_size=4)
diff --git a/compiler/tests/07_column_mux_array_2mux_1rw_1r_test.py b/compiler/tests/07_column_mux_array_2mux_1rw_1r_test.py
index f217720e..c284158b 100755
--- a/compiler/tests/07_column_mux_array_2mux_1rw_1r_test.py
+++ b/compiler/tests/07_column_mux_array_2mux_1rw_1r_test.py
@@ -19,7 +19,7 @@ class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/07_column_mux_array_2mux_test.py b/compiler/tests/07_column_mux_array_2mux_test.py
index ba5145a4..8377bff8 100755
--- a/compiler/tests/07_column_mux_array_2mux_test.py
+++ b/compiler/tests/07_column_mux_array_2mux_test.py
@@ -19,7 +19,7 @@ class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for 2-way column_mux_array")
         a = factory.create(module_type="column_mux_array", columns=16, word_size=8)
diff --git a/compiler/tests/07_column_mux_array_4mux_1rw_1r_test.py b/compiler/tests/07_column_mux_array_4mux_1rw_1r_test.py
index 8f4fc364..4487e3ea 100755
--- a/compiler/tests/07_column_mux_array_4mux_1rw_1r_test.py
+++ b/compiler/tests/07_column_mux_array_4mux_1rw_1r_test.py
@@ -19,7 +19,7 @@ class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/07_column_mux_array_4mux_test.py b/compiler/tests/07_column_mux_array_4mux_test.py
index 0d637ef6..e5b5b140 100755
--- a/compiler/tests/07_column_mux_array_4mux_test.py
+++ b/compiler/tests/07_column_mux_array_4mux_test.py
@@ -19,7 +19,7 @@ class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for 4-way column_mux_array")
         a = factory.create(module_type="column_mux_array", columns=16, word_size=4)
diff --git a/compiler/tests/07_column_mux_array_8mux_1rw_1r_test.py b/compiler/tests/07_column_mux_array_8mux_1rw_1r_test.py
index 7d2f248e..55a0df95 100755
--- a/compiler/tests/07_column_mux_array_8mux_1rw_1r_test.py
+++ b/compiler/tests/07_column_mux_array_8mux_1rw_1r_test.py
@@ -19,7 +19,7 @@ class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/07_column_mux_array_8mux_test.py b/compiler/tests/07_column_mux_array_8mux_test.py
index 468d6507..18669aac 100755
--- a/compiler/tests/07_column_mux_array_8mux_test.py
+++ b/compiler/tests/07_column_mux_array_8mux_test.py
@@ -19,7 +19,7 @@ class column_mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for 8-way column_mux_array")
         a = factory.create(module_type="column_mux_array", columns=32, word_size=4)
diff --git a/compiler/tests/07_column_mux_array_pbitcell_test.py b/compiler/tests/07_column_mux_array_pbitcell_test.py
index bceba919..d406261d 100755
--- a/compiler/tests/07_column_mux_array_pbitcell_test.py
+++ b/compiler/tests/07_column_mux_array_pbitcell_test.py
@@ -19,7 +19,7 @@ class column_mux_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check single level column mux array in multi-port
         OPTS.bitcell = "pbitcell"
diff --git a/compiler/tests/08_precharge_array_1rw_1r_test.py b/compiler/tests/08_precharge_array_1rw_1r_test.py
index 1cb4d12c..1c185466 100755
--- a/compiler/tests/08_precharge_array_1rw_1r_test.py
+++ b/compiler/tests/08_precharge_array_1rw_1r_test.py
@@ -20,7 +20,7 @@ class precharge_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check precharge array in multi-port
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/08_precharge_array_test.py b/compiler/tests/08_precharge_array_test.py
index 39d87476..b63b731e 100755
--- a/compiler/tests/08_precharge_array_test.py
+++ b/compiler/tests/08_precharge_array_test.py
@@ -19,7 +19,7 @@ class precharge_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Checking 3 column precharge")
         pc = factory.create(module_type="precharge_array", columns=3)
diff --git a/compiler/tests/08_wordline_buffer_array_test.py b/compiler/tests/08_wordline_buffer_array_test.py
index 6ae422c4..90b20d9b 100755
--- a/compiler/tests/08_wordline_buffer_array_test.py
+++ b/compiler/tests/08_wordline_buffer_array_test.py
@@ -20,7 +20,7 @@ class wordline_buffer_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check wordline driver for single port
         debug.info(2, "Checking driver")
diff --git a/compiler/tests/08_wordline_driver_array_1rw_1r_test.py b/compiler/tests/08_wordline_driver_array_1rw_1r_test.py
index cbfa1825..d1b837ca 100755
--- a/compiler/tests/08_wordline_driver_array_1rw_1r_test.py
+++ b/compiler/tests/08_wordline_driver_array_1rw_1r_test.py
@@ -20,7 +20,7 @@ class wordline_driver_array_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # Use the 2 port cell since it is usually bigger/easier
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/08_wordline_driver_array_pbitcell_test.py b/compiler/tests/08_wordline_driver_array_pbitcell_test.py
index f3398346..a49321e1 100755
--- a/compiler/tests/08_wordline_driver_array_pbitcell_test.py
+++ b/compiler/tests/08_wordline_driver_array_pbitcell_test.py
@@ -20,7 +20,7 @@ class wordline_driver_array_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check wordline driver for multi-port
         OPTS.bitcell = "pbitcell"
diff --git a/compiler/tests/08_wordline_driver_array_test.py b/compiler/tests/08_wordline_driver_array_test.py
index ea982005..62d41506 100755
--- a/compiler/tests/08_wordline_driver_array_test.py
+++ b/compiler/tests/08_wordline_driver_array_test.py
@@ -20,7 +20,7 @@ class wordline_driver_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check wordline driver for single port
         debug.info(2, "Checking driver")
diff --git a/compiler/tests/09_sense_amp_array_1rw_1r_test.py b/compiler/tests/09_sense_amp_array_1rw_1r_test.py
index 8273a0ad..9af9ff54 100755
--- a/compiler/tests/09_sense_amp_array_1rw_1r_test.py
+++ b/compiler/tests/09_sense_amp_array_1rw_1r_test.py
@@ -20,7 +20,7 @@ class sense_amp_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/09_sense_amp_array_pbitcell_test.py b/compiler/tests/09_sense_amp_array_pbitcell_test.py
index 4dfd966d..5d5f89b5 100755
--- a/compiler/tests/09_sense_amp_array_pbitcell_test.py
+++ b/compiler/tests/09_sense_amp_array_pbitcell_test.py
@@ -19,7 +19,7 @@ class sense_amp_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         #check sense amp array for multi-port
         OPTS.bitcell = "pbitcell"
diff --git a/compiler/tests/09_sense_amp_array_spare_cols_test.py b/compiler/tests/09_sense_amp_array_spare_cols_test.py
index 57429d2b..06db38ba 100755
--- a/compiler/tests/09_sense_amp_array_spare_cols_test.py
+++ b/compiler/tests/09_sense_amp_array_spare_cols_test.py
@@ -19,7 +19,7 @@ class sense_amp_array_spare_cols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check sense amp array for single port
         debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 and num_spare_cols=3")
diff --git a/compiler/tests/09_sense_amp_array_test.py b/compiler/tests/09_sense_amp_array_test.py
index aa21f181..7af1481f 100755
--- a/compiler/tests/09_sense_amp_array_test.py
+++ b/compiler/tests/09_sense_amp_array_test.py
@@ -19,7 +19,7 @@ class sense_amp_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=1")
         a = factory.create(module_type="sense_amp_array", word_size=4, words_per_row=1)
diff --git a/compiler/tests/10_write_driver_array_1rw_1r_test.py b/compiler/tests/10_write_driver_array_1rw_1r_test.py
index 534d5904..6a3ae1c1 100755
--- a/compiler/tests/10_write_driver_array_1rw_1r_test.py
+++ b/compiler/tests/10_write_driver_array_1rw_1r_test.py
@@ -20,7 +20,7 @@ class write_driver_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/10_write_driver_array_pbitcell_test.py b/compiler/tests/10_write_driver_array_pbitcell_test.py
index cd5601ce..2a757a2b 100755
--- a/compiler/tests/10_write_driver_array_pbitcell_test.py
+++ b/compiler/tests/10_write_driver_array_pbitcell_test.py
@@ -19,7 +19,7 @@ class write_driver_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for multi-port
         OPTS.bitcell = "pbitcell"
diff --git a/compiler/tests/10_write_driver_array_spare_cols_test.py b/compiler/tests/10_write_driver_array_spare_cols_test.py
index bacfbdd9..c8c7a923 100755
--- a/compiler/tests/10_write_driver_array_spare_cols_test.py
+++ b/compiler/tests/10_write_driver_array_spare_cols_test.py
@@ -19,7 +19,7 @@ class write_driver_array_spare_cols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for single port
         debug.info(2, "Testing write_driver_array for columns=8, word_size=8 and num_spare_cols=3")
diff --git a/compiler/tests/10_write_driver_array_test.py b/compiler/tests/10_write_driver_array_test.py
index fc17301e..8195990c 100755
--- a/compiler/tests/10_write_driver_array_test.py
+++ b/compiler/tests/10_write_driver_array_test.py
@@ -19,7 +19,7 @@ class write_driver_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for single port
         debug.info(2, "Testing write_driver_array for columns=8, word_size=8")
diff --git a/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py b/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py
index 02c76300..cd4ed505 100755
--- a/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py
+++ b/compiler/tests/10_write_driver_array_wmask_pbitcell_test.py
@@ -21,7 +21,7 @@ class write_driver_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for multi-port
         OPTS.bitcell = "pbitcell"
diff --git a/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py b/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py
index e609ba43..e7964983 100755
--- a/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py
+++ b/compiler/tests/10_write_driver_array_wmask_spare_cols_test.py
@@ -21,7 +21,7 @@ class write_driver_array_wmask_spare_cols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for single port
         debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4")
diff --git a/compiler/tests/10_write_driver_array_wmask_test.py b/compiler/tests/10_write_driver_array_wmask_test.py
index 7c1fd7bc..f2767690 100755
--- a/compiler/tests/10_write_driver_array_wmask_test.py
+++ b/compiler/tests/10_write_driver_array_wmask_test.py
@@ -21,7 +21,7 @@ class write_driver_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for single port
         debug.info(2, "Testing write_driver_array for columns=8, word_size=8, write_size=4")
diff --git a/compiler/tests/10_write_mask_and_array_1rw_1r_test.py b/compiler/tests/10_write_mask_and_array_1rw_1r_test.py
index 806381b5..d90cc0a2 100755
--- a/compiler/tests/10_write_mask_and_array_1rw_1r_test.py
+++ b/compiler/tests/10_write_mask_and_array_1rw_1r_test.py
@@ -20,7 +20,7 @@ class write_mask_and_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/10_write_mask_and_array_pbitcell_test.py b/compiler/tests/10_write_mask_and_array_pbitcell_test.py
index fe43d0f2..e3d8fd84 100755
--- a/compiler/tests/10_write_mask_and_array_pbitcell_test.py
+++ b/compiler/tests/10_write_mask_and_array_pbitcell_test.py
@@ -21,7 +21,7 @@ class write_mask_and_array_pbitcell_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for multi-port
         OPTS.bitcell = "pbitcell"
diff --git a/compiler/tests/10_write_mask_and_array_test.py b/compiler/tests/10_write_mask_and_array_test.py
index 8a667145..1b9dcd28 100755
--- a/compiler/tests/10_write_mask_and_array_test.py
+++ b/compiler/tests/10_write_mask_and_array_test.py
@@ -21,7 +21,7 @@ class write_mask_and_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check write driver array for single port
         debug.info(2, "Testing write_mask_and_array for columns=8, word_size=8, write_size=4")
diff --git a/compiler/tests/11_dff_array_test.py b/compiler/tests/11_dff_array_test.py
index 7d4779eb..32383548 100755
--- a/compiler/tests/11_dff_array_test.py
+++ b/compiler/tests/11_dff_array_test.py
@@ -19,7 +19,7 @@ class dff_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing dff_array for 3x3")
         a = factory.create(module_type="dff_array", rows=3, columns=3)
diff --git a/compiler/tests/11_dff_buf_array_test.py b/compiler/tests/11_dff_buf_array_test.py
index e46a5f91..ca357666 100755
--- a/compiler/tests/11_dff_buf_array_test.py
+++ b/compiler/tests/11_dff_buf_array_test.py
@@ -19,7 +19,7 @@ class dff_buf_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing dff_buf_array for 3x3")
         a = factory.create(module_type="dff_buf_array", rows=3, columns=3)
diff --git a/compiler/tests/12_tri_gate_array_test.py b/compiler/tests/12_tri_gate_array_test.py
index 354e5188..673dc884 100755
--- a/compiler/tests/12_tri_gate_array_test.py
+++ b/compiler/tests/12_tri_gate_array_test.py
@@ -21,7 +21,7 @@ class tri_gate_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing tri_gate_array for columns=8, word_size=8")
         a = factory.create(module_type="tri_gate_array", columns=8, word_size=8)
diff --git a/compiler/tests/13_delay_chain_test.py b/compiler/tests/13_delay_chain_test.py
index b07dde74..563565a8 100755
--- a/compiler/tests/13_delay_chain_test.py
+++ b/compiler/tests/13_delay_chain_test.py
@@ -19,7 +19,7 @@ class delay_chain_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing delay_chain")
         a = factory.create(module_type="delay_chain", fanout_list=[4, 4, 4, 4])
diff --git a/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py
index 0f905d75..0f85caca 100755
--- a/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py
+++ b/compiler/tests/14_replica_bitcell_array_bothrbl_1rw_1r_test.py
@@ -18,7 +18,7 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py
index a07318f0..2cb9f7c0 100755
--- a/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py
+++ b/compiler/tests/14_replica_bitcell_array_leftrbl_1rw_1r_test.py
@@ -18,7 +18,7 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py b/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py
index 920a3d3e..abe0b40d 100755
--- a/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py
+++ b/compiler/tests/14_replica_bitcell_array_norbl_1rw_1r_test.py
@@ -18,7 +18,7 @@ class replica_bitcell_array_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/14_replica_bitcell_array_test.py b/compiler/tests/14_replica_bitcell_array_test.py
index fc938bfb..8b754cf2 100755
--- a/compiler/tests/14_replica_bitcell_array_test.py
+++ b/compiler/tests/14_replica_bitcell_array_test.py
@@ -17,7 +17,7 @@ class replica_bitcell_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 0
diff --git a/compiler/tests/14_replica_column_1rw_1r_test.py b/compiler/tests/14_replica_column_1rw_1r_test.py
index 6d67bef9..eab07b2a 100755
--- a/compiler/tests/14_replica_column_1rw_1r_test.py
+++ b/compiler/tests/14_replica_column_1rw_1r_test.py
@@ -18,7 +18,7 @@ class replica_column_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/14_replica_column_test.py b/compiler/tests/14_replica_column_test.py
index 73825e39..77f49dab 100755
--- a/compiler/tests/14_replica_column_test.py
+++ b/compiler/tests/14_replica_column_test.py
@@ -18,7 +18,7 @@ class replica_column_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         if OPTS.tech_name == "sky130":
             num_spare_rows = 1
             num_spare_cols = 1
diff --git a/compiler/tests/14_replica_pbitcell_array_test.py b/compiler/tests/14_replica_pbitcell_array_test.py
index d72289a7..328b2d90 100755
--- a/compiler/tests/14_replica_pbitcell_array_test.py
+++ b/compiler/tests/14_replica_pbitcell_array_test.py
@@ -17,7 +17,7 @@ class replica_pbitcell_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.bitcell = "pbitcell"
         OPTS.replica_bitcell = "replica_pbitcell"
diff --git a/compiler/tests/15_global_bitcell_array_1rw_1r_test.py b/compiler/tests/15_global_bitcell_array_1rw_1r_test.py
index d7701539..5e9589ff 100755
--- a/compiler/tests/15_global_bitcell_array_1rw_1r_test.py
+++ b/compiler/tests/15_global_bitcell_array_1rw_1r_test.py
@@ -20,7 +20,7 @@ class global_bitcell_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/15_global_bitcell_array_test.py b/compiler/tests/15_global_bitcell_array_test.py
index 7f4b8154..e49806c0 100755
--- a/compiler/tests/15_global_bitcell_array_test.py
+++ b/compiler/tests/15_global_bitcell_array_test.py
@@ -20,7 +20,7 @@ class global_bitcell_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # debug.info(2, "Testing 2 x 4x4 global bitcell array for 6t_cell")
         # a = factory.create(module_type="global_bitcell_array", cols=[4, 4], rows=4)
diff --git a/compiler/tests/15_local_bitcell_array_1rw_1r_test.py b/compiler/tests/15_local_bitcell_array_1rw_1r_test.py
index 0826586c..ce4636b8 100755
--- a/compiler/tests/15_local_bitcell_array_1rw_1r_test.py
+++ b/compiler/tests/15_local_bitcell_array_1rw_1r_test.py
@@ -20,7 +20,7 @@ class local_bitcell_array_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         OPTS.num_rw_ports = 1
         OPTS.num_r_ports = 1
diff --git a/compiler/tests/15_local_bitcell_array_test.py b/compiler/tests/15_local_bitcell_array_test.py
index 30c9c8e9..699f3e9f 100755
--- a/compiler/tests/15_local_bitcell_array_test.py
+++ b/compiler/tests/15_local_bitcell_array_test.py
@@ -20,7 +20,7 @@ class local_bitcell_array_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(2, "Testing 4x4 local bitcell array for 6t_cell without replica")
         a = factory.create(module_type="local_bitcell_array", cols=4, rows=4, rbl=[1, 0])
diff --git a/compiler/tests/16_control_logic_multiport_test.py b/compiler/tests/16_control_logic_multiport_test.py
index ae6ce538..71c88dee 100755
--- a/compiler/tests/16_control_logic_multiport_test.py
+++ b/compiler/tests/16_control_logic_multiport_test.py
@@ -23,7 +23,7 @@ class control_logic_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # check control logic for multi-port
         OPTS.bitcell = "pbitcell"
diff --git a/compiler/tests/16_control_logic_r_test.py b/compiler/tests/16_control_logic_r_test.py
index 67fa2635..478acaa9 100755
--- a/compiler/tests/16_control_logic_r_test.py
+++ b/compiler/tests/16_control_logic_r_test.py
@@ -20,7 +20,7 @@ class control_logic_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for control_logic_r")
         a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, port_type="r")
diff --git a/compiler/tests/16_control_logic_rw_test.py b/compiler/tests/16_control_logic_rw_test.py
index dd83f623..3c0304d6 100755
--- a/compiler/tests/16_control_logic_rw_test.py
+++ b/compiler/tests/16_control_logic_rw_test.py
@@ -20,7 +20,7 @@ class control_logic_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for control_logic_rw")
         a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32)
diff --git a/compiler/tests/16_control_logic_w_test.py b/compiler/tests/16_control_logic_w_test.py
index 4a828fdf..ef426398 100755
--- a/compiler/tests/16_control_logic_w_test.py
+++ b/compiler/tests/16_control_logic_w_test.py
@@ -19,7 +19,7 @@ class control_logic_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing sample for control_logic_w")
         a = factory.create(module_type="control_logic", num_rows=128, words_per_row=1, word_size=32, port_type="w")
diff --git a/compiler/tests/18_port_address_16rows_1rw_1r_test.py b/compiler/tests/18_port_address_16rows_1rw_1r_test.py
index ffca57d3..eacf8da7 100755
--- a/compiler/tests/18_port_address_16rows_1rw_1r_test.py
+++ b/compiler/tests/18_port_address_16rows_1rw_1r_test.py
@@ -18,7 +18,7 @@ class port_address_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # Use the 2 port cell since it is usually bigger/easier
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/18_port_address_16rows_test.py b/compiler/tests/18_port_address_16rows_test.py
index 36093297..20edcbd9 100755
--- a/compiler/tests/18_port_address_16rows_test.py
+++ b/compiler/tests/18_port_address_16rows_test.py
@@ -18,7 +18,7 @@ class port_address_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Port address 16 rows")
         a = factory.create("port_address", cols=16, rows=16, port=0)
diff --git a/compiler/tests/18_port_address_256rows_1rw_1r_test.py b/compiler/tests/18_port_address_256rows_1rw_1r_test.py
index 8fef71fc..53307e21 100755
--- a/compiler/tests/18_port_address_256rows_1rw_1r_test.py
+++ b/compiler/tests/18_port_address_256rows_1rw_1r_test.py
@@ -18,7 +18,7 @@ class port_address_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         # Use the 2 port cell since it is usually bigger/easier
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/18_port_address_512rows_test.py b/compiler/tests/18_port_address_512rows_test.py
index 03f8c455..5e610074 100755
--- a/compiler/tests/18_port_address_512rows_test.py
+++ b/compiler/tests/18_port_address_512rows_test.py
@@ -18,7 +18,7 @@ class port_address_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Port address 512 rows")
         a = factory.create("port_address", cols=256, rows=512, port=0)
diff --git a/compiler/tests/18_port_data_16mux_1rw_1r_test.py b/compiler/tests/18_port_data_16mux_1rw_1r_test.py
index 15ff8eee..9b5401da 100755
--- a/compiler/tests/18_port_data_16mux_1rw_1r_test.py
+++ b/compiler/tests/18_port_data_16mux_1rw_1r_test.py
@@ -18,7 +18,7 @@ class port_data_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/18_port_data_16mux_test.py b/compiler/tests/18_port_data_16mux_test.py
index 3415711b..2a374b8e 100755
--- a/compiler/tests/18_port_data_16mux_test.py
+++ b/compiler/tests/18_port_data_16mux_test.py
@@ -18,7 +18,7 @@ class port_data_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         if OPTS.tech_name == "sky130":
diff --git a/compiler/tests/18_port_data_2mux_1rw_1r_test.py b/compiler/tests/18_port_data_2mux_1rw_1r_test.py
index d907b50c..b47d1fbb 100755
--- a/compiler/tests/18_port_data_2mux_1rw_1r_test.py
+++ b/compiler/tests/18_port_data_2mux_1rw_1r_test.py
@@ -18,7 +18,7 @@ class port_data_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/18_port_data_2mux_test.py b/compiler/tests/18_port_data_2mux_test.py
index 4b72d046..4498500f 100755
--- a/compiler/tests/18_port_data_2mux_test.py
+++ b/compiler/tests/18_port_data_2mux_test.py
@@ -18,7 +18,7 @@ class port_data_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         if OPTS.tech_name == "sky130":
diff --git a/compiler/tests/18_port_data_4mux_1rw_1r_test.py b/compiler/tests/18_port_data_4mux_1rw_1r_test.py
index c5d163cf..b78751f4 100755
--- a/compiler/tests/18_port_data_4mux_1rw_1r_test.py
+++ b/compiler/tests/18_port_data_4mux_1rw_1r_test.py
@@ -18,7 +18,7 @@ class port_data_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/18_port_data_4mux_test.py b/compiler/tests/18_port_data_4mux_test.py
index 84136361..f3e4ae67 100755
--- a/compiler/tests/18_port_data_4mux_test.py
+++ b/compiler/tests/18_port_data_4mux_test.py
@@ -18,7 +18,7 @@ class port_data_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         if OPTS.tech_name == "sky130":
diff --git a/compiler/tests/18_port_data_8mux_1rw_1r_test.py b/compiler/tests/18_port_data_8mux_1rw_1r_test.py
index 17c98ace..165a83f7 100755
--- a/compiler/tests/18_port_data_8mux_1rw_1r_test.py
+++ b/compiler/tests/18_port_data_8mux_1rw_1r_test.py
@@ -18,7 +18,7 @@ class port_data_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/18_port_data_8mux_test.py b/compiler/tests/18_port_data_8mux_test.py
index 781954cc..b74809a2 100755
--- a/compiler/tests/18_port_data_8mux_test.py
+++ b/compiler/tests/18_port_data_8mux_test.py
@@ -18,7 +18,7 @@ class port_data_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         if OPTS.tech_name == "sky130":
diff --git a/compiler/tests/18_port_data_nomux_1rw_1r_test.py b/compiler/tests/18_port_data_nomux_1rw_1r_test.py
index 1c1197ee..4ec876c8 100755
--- a/compiler/tests/18_port_data_nomux_1rw_1r_test.py
+++ b/compiler/tests/18_port_data_nomux_1rw_1r_test.py
@@ -18,7 +18,7 @@ class port_data_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/18_port_data_nomux_test.py b/compiler/tests/18_port_data_nomux_test.py
index 7d775cd5..871b0036 100755
--- a/compiler/tests/18_port_data_nomux_test.py
+++ b/compiler/tests/18_port_data_nomux_test.py
@@ -18,7 +18,7 @@ class port_data_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         if OPTS.tech_name == "sky130":
diff --git a/compiler/tests/18_port_data_spare_cols_test.py b/compiler/tests/18_port_data_spare_cols_test.py
index e26be6e8..64b66a96 100755
--- a/compiler/tests/18_port_data_spare_cols_test.py
+++ b/compiler/tests/18_port_data_spare_cols_test.py
@@ -18,7 +18,7 @@ class port_data_spare_cols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         c = sram_config(word_size=8,
diff --git a/compiler/tests/18_port_data_wmask_1rw_1r_test.py b/compiler/tests/18_port_data_wmask_1rw_1r_test.py
index 5f58f670..77741cc3 100755
--- a/compiler/tests/18_port_data_wmask_1rw_1r_test.py
+++ b/compiler/tests/18_port_data_wmask_1rw_1r_test.py
@@ -18,7 +18,7 @@ class port_data_wmask_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/18_port_data_wmask_test.py b/compiler/tests/18_port_data_wmask_test.py
index 406b6822..2d206aac 100755
--- a/compiler/tests/18_port_data_wmask_test.py
+++ b/compiler/tests/18_port_data_wmask_test.py
@@ -19,7 +19,7 @@ class port_data_wmask_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         if OPTS.tech_name == "sky130":
diff --git a/compiler/tests/19_multi_bank_test.py b/compiler/tests/19_multi_bank_test.py
index e73a97fc..2ebb9035 100755
--- a/compiler/tests/19_multi_bank_test.py
+++ b/compiler/tests/19_multi_bank_test.py
@@ -20,7 +20,7 @@ class multi_bank_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         c = sram_config(word_size=4,
diff --git a/compiler/tests/19_pmulti_bank_test.py b/compiler/tests/19_pmulti_bank_test.py
index be2ba0c0..5749c0dd 100755
--- a/compiler/tests/19_pmulti_bank_test.py
+++ b/compiler/tests/19_pmulti_bank_test.py
@@ -20,7 +20,7 @@ class multi_bank_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
         OPTS.bitcell = "pbitcell"
 
diff --git a/compiler/tests/19_psingle_bank_test.py b/compiler/tests/19_psingle_bank_test.py
index 539ebbc0..61cbd91a 100755
--- a/compiler/tests/19_psingle_bank_test.py
+++ b/compiler/tests/19_psingle_bank_test.py
@@ -20,7 +20,7 @@ class psingle_bank_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.bitcell = "pbitcell"
diff --git a/compiler/tests/19_single_bank_16mux_1rw_1r_test.py b/compiler/tests/19_single_bank_16mux_1rw_1r_test.py
index adc5d33e..027e48a1 100755
--- a/compiler/tests/19_single_bank_16mux_1rw_1r_test.py
+++ b/compiler/tests/19_single_bank_16mux_1rw_1r_test.py
@@ -20,7 +20,7 @@ class single_bank_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/19_single_bank_16mux_test.py b/compiler/tests/19_single_bank_16mux_test.py
index 8dd02db3..f77a9a27 100755
--- a/compiler/tests/19_single_bank_16mux_test.py
+++ b/compiler/tests/19_single_bank_16mux_test.py
@@ -20,7 +20,7 @@ class single_bank_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         if OPTS.tech_name == "sky130":
diff --git a/compiler/tests/19_single_bank_1w_1r_test.py b/compiler/tests/19_single_bank_1w_1r_test.py
index 31b8349b..2b6829e4 100755
--- a/compiler/tests/19_single_bank_1w_1r_test.py
+++ b/compiler/tests/19_single_bank_1w_1r_test.py
@@ -20,7 +20,7 @@ class single_bank_1w_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 0
diff --git a/compiler/tests/19_single_bank_2mux_1rw_1r_test.py b/compiler/tests/19_single_bank_2mux_1rw_1r_test.py
index dbed3cc6..76275e98 100755
--- a/compiler/tests/19_single_bank_2mux_1rw_1r_test.py
+++ b/compiler/tests/19_single_bank_2mux_1rw_1r_test.py
@@ -20,7 +20,7 @@ class single_bank_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/19_single_bank_2mux_test.py b/compiler/tests/19_single_bank_2mux_test.py
index f5efc231..83e48e00 100755
--- a/compiler/tests/19_single_bank_2mux_test.py
+++ b/compiler/tests/19_single_bank_2mux_test.py
@@ -20,7 +20,7 @@ class single_bank_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         c = sram_config(word_size=4,
diff --git a/compiler/tests/19_single_bank_4mux_1rw_1r_test.py b/compiler/tests/19_single_bank_4mux_1rw_1r_test.py
index 13387ac9..57bed230 100755
--- a/compiler/tests/19_single_bank_4mux_1rw_1r_test.py
+++ b/compiler/tests/19_single_bank_4mux_1rw_1r_test.py
@@ -20,7 +20,7 @@ class single_bank_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/19_single_bank_4mux_test.py b/compiler/tests/19_single_bank_4mux_test.py
index 7a58b401..d5cbf640 100755
--- a/compiler/tests/19_single_bank_4mux_test.py
+++ b/compiler/tests/19_single_bank_4mux_test.py
@@ -20,7 +20,7 @@ class single_bank_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         c = sram_config(word_size=4,
diff --git a/compiler/tests/19_single_bank_8mux_1rw_1r_test.py b/compiler/tests/19_single_bank_8mux_1rw_1r_test.py
index f03aadc6..01d65bdc 100755
--- a/compiler/tests/19_single_bank_8mux_1rw_1r_test.py
+++ b/compiler/tests/19_single_bank_8mux_1rw_1r_test.py
@@ -20,7 +20,7 @@ class single_bank_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/19_single_bank_8mux_test.py b/compiler/tests/19_single_bank_8mux_test.py
index 56a3c549..46dfdfcd 100755
--- a/compiler/tests/19_single_bank_8mux_test.py
+++ b/compiler/tests/19_single_bank_8mux_test.py
@@ -20,7 +20,7 @@ class single_bank_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         if OPTS.tech_name == "sky130":
diff --git a/compiler/tests/19_single_bank_global_bitline_test.py b/compiler/tests/19_single_bank_global_bitline_test.py
index ead8decb..e3f942a6 100755
--- a/compiler/tests/19_single_bank_global_bitline_test.py
+++ b/compiler/tests/19_single_bank_global_bitline_test.py
@@ -20,7 +20,7 @@ class single_bank_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/19_single_bank_nomux_1rw_1r_test.py b/compiler/tests/19_single_bank_nomux_1rw_1r_test.py
index afb1129b..ff31abe8 100755
--- a/compiler/tests/19_single_bank_nomux_1rw_1r_test.py
+++ b/compiler/tests/19_single_bank_nomux_1rw_1r_test.py
@@ -20,7 +20,7 @@ class single_bank_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/19_single_bank_nomux_test.py b/compiler/tests/19_single_bank_nomux_test.py
index 6ae084ec..21724707 100755
--- a/compiler/tests/19_single_bank_nomux_test.py
+++ b/compiler/tests/19_single_bank_nomux_test.py
@@ -20,7 +20,7 @@ class single_bank_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         if OPTS.tech_name == "sky130":
diff --git a/compiler/tests/19_single_bank_spare_cols_test.py b/compiler/tests/19_single_bank_spare_cols_test.py
index 97bcf5af..e52aba5d 100755
--- a/compiler/tests/19_single_bank_spare_cols_test.py
+++ b/compiler/tests/19_single_bank_spare_cols_test.py
@@ -19,7 +19,7 @@ class single_bank_spare_cols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         c = sram_config(word_size=4,
diff --git a/compiler/tests/19_single_bank_wmask_1rw_1r_test.py b/compiler/tests/19_single_bank_wmask_1rw_1r_test.py
index 77f7ba2e..908e6655 100755
--- a/compiler/tests/19_single_bank_wmask_1rw_1r_test.py
+++ b/compiler/tests/19_single_bank_wmask_1rw_1r_test.py
@@ -20,7 +20,7 @@ class single_bank_wmask_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/19_single_bank_wmask_test.py b/compiler/tests/19_single_bank_wmask_test.py
index 08fe19f4..3c33229d 100755
--- a/compiler/tests/19_single_bank_wmask_test.py
+++ b/compiler/tests/19_single_bank_wmask_test.py
@@ -19,7 +19,7 @@ class single_bank_wmask_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
 
diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py
index 0c24ff3b..1cb73747 100755
--- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py
+++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py
@@ -20,7 +20,7 @@ class psram_1bank_2mux_1rw_1w_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.bitcell = "pbitcell"
diff --git a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py
index c8606bae..46c27735 100755
--- a/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py
+++ b/compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py
@@ -20,7 +20,7 @@ class psram_1bank_2mux_1rw_1w_wmask_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.bitcell = "pbitcell"
diff --git a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py
index 51be2cab..2c683be4 100755
--- a/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py
+++ b/compiler/tests/20_psram_1bank_2mux_1w_1r_test.py
@@ -20,7 +20,7 @@ class psram_1bank_2mux_1w_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.bitcell = "pbitcell"
diff --git a/compiler/tests/20_psram_1bank_2mux_test.py b/compiler/tests/20_psram_1bank_2mux_test.py
index 133c81d1..25a4f8b1 100755
--- a/compiler/tests/20_psram_1bank_2mux_test.py
+++ b/compiler/tests/20_psram_1bank_2mux_test.py
@@ -20,7 +20,7 @@ class psram_1bank_2mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.bitcell = "pbitcell"
diff --git a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py
index 0995e49f..7c6a1b10 100755
--- a/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py
+++ b/compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py
@@ -20,7 +20,7 @@ class psram_1bank_4mux_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.bitcell = "pbitcell"
diff --git a/compiler/tests/20_sram_1bank_16mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_16mux_1rw_1r_test.py
index 93736a53..0440c535 100755
--- a/compiler/tests/20_sram_1bank_16mux_1rw_1r_test.py
+++ b/compiler/tests/20_sram_1bank_16mux_1rw_1r_test.py
@@ -20,7 +20,7 @@ class sram_1bank_8mux_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/20_sram_1bank_16mux_test.py b/compiler/tests/20_sram_1bank_16mux_test.py
index 6461c5a6..a507544d 100755
--- a/compiler/tests/20_sram_1bank_16mux_test.py
+++ b/compiler/tests/20_sram_1bank_16mux_test.py
@@ -20,7 +20,7 @@ class sram_1bank_8mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         if OPTS.tech_name == "sky130":
diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py
index 08922ede..b59a76ed 100755
--- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py
+++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py
@@ -20,7 +20,7 @@ class sram_1bank_2mux_1rw_1r_spare_cols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py
index b5d9d776..4dcc5191 100755
--- a/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py
+++ b/compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py
@@ -20,7 +20,7 @@ class sram_1bank_2mux_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py
index abbb2347..e4ba034c 100755
--- a/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py
+++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py
@@ -20,7 +20,7 @@ class sram_1bank_2mux_1w_1r_spare_cols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 0
diff --git a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py
index 5eabef8b..5627550d 100755
--- a/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py
+++ b/compiler/tests/20_sram_1bank_2mux_1w_1r_test.py
@@ -20,7 +20,7 @@ class psram_1bank_2mux_1w_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 0
diff --git a/compiler/tests/20_sram_1bank_2mux_global_test.py b/compiler/tests/20_sram_1bank_2mux_global_test.py
index fc4a32e8..92df8a59 100755
--- a/compiler/tests/20_sram_1bank_2mux_global_test.py
+++ b/compiler/tests/20_sram_1bank_2mux_global_test.py
@@ -20,7 +20,7 @@ class sram_1bank_2mux_global_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
         OPTS.local_array_size = 8
 
diff --git a/compiler/tests/20_sram_1bank_2mux_test.py b/compiler/tests/20_sram_1bank_2mux_test.py
index 85041348..df69288f 100755
--- a/compiler/tests/20_sram_1bank_2mux_test.py
+++ b/compiler/tests/20_sram_1bank_2mux_test.py
@@ -20,7 +20,7 @@ class sram_1bank_2mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         if OPTS.tech_name == "sky130":
diff --git a/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py b/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py
index d24fa62f..cb650308 100755
--- a/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py
+++ b/compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py
@@ -20,7 +20,7 @@ class sram_1bank_2mux_wmask_spare_cols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         if OPTS.tech_name == "sky130":
diff --git a/compiler/tests/20_sram_1bank_2mux_wmask_test.py b/compiler/tests/20_sram_1bank_2mux_wmask_test.py
index 84830d5c..6b322eac 100755
--- a/compiler/tests/20_sram_1bank_2mux_wmask_test.py
+++ b/compiler/tests/20_sram_1bank_2mux_wmask_test.py
@@ -20,7 +20,7 @@ class sram_1bank_2mux_wmask_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         if OPTS.tech_name == "sky130":
diff --git a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py
index 4df1bcca..9a53d04c 100755
--- a/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py
+++ b/compiler/tests/20_sram_1bank_32b_1024_wmask_test.py
@@ -21,7 +21,7 @@ class sram_1bank_32b_1024_wmask_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         if OPTS.tech_name == "sky130":
diff --git a/compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py
index 905bf1e4..8224c372 100755
--- a/compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py
+++ b/compiler/tests/20_sram_1bank_4mux_1rw_1r_test.py
@@ -20,7 +20,7 @@ class sram_1bank_4mux_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/20_sram_1bank_4mux_test.py b/compiler/tests/20_sram_1bank_4mux_test.py
index 0fdf883a..c505258d 100755
--- a/compiler/tests/20_sram_1bank_4mux_test.py
+++ b/compiler/tests/20_sram_1bank_4mux_test.py
@@ -20,7 +20,7 @@ class sram_1bank_4mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         if OPTS.tech_name == "sky130":
diff --git a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py
index bc1f824d..a6e6ffc6 100755
--- a/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py
+++ b/compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py
@@ -20,7 +20,7 @@ class sram_1bank_8mux_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/20_sram_1bank_8mux_test.py b/compiler/tests/20_sram_1bank_8mux_test.py
index a670744a..d32da29f 100755
--- a/compiler/tests/20_sram_1bank_8mux_test.py
+++ b/compiler/tests/20_sram_1bank_8mux_test.py
@@ -20,7 +20,7 @@ class sram_1bank_8mux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         if OPTS.tech_name == "sky130":
diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py
index 561074a1..89c2e8b7 100755
--- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py
+++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py
@@ -20,7 +20,7 @@ class sram_1bank_nomux_1rw_1r_spare_cols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py
index e8e18b7a..2e54fda0 100755
--- a/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py
+++ b/compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py
@@ -20,7 +20,7 @@ class sram_1bank_nomux_1rw_1r_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py b/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py
index 99131037..2e7c9c70 100755
--- a/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py
+++ b/compiler/tests/20_sram_1bank_nomux_spare_cols_test.py
@@ -20,7 +20,7 @@ class sram_1bank_nomux_spare_cols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         if OPTS.tech_name == "sky130":
diff --git a/compiler/tests/20_sram_1bank_nomux_test.py b/compiler/tests/20_sram_1bank_nomux_test.py
index 59e309df..a1440ab2 100755
--- a/compiler/tests/20_sram_1bank_nomux_test.py
+++ b/compiler/tests/20_sram_1bank_nomux_test.py
@@ -19,7 +19,7 @@ class sram_1bank_nomux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         if OPTS.tech_name == "sky130":
diff --git a/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py b/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py
index a7326df3..87631004 100755
--- a/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py
+++ b/compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py
@@ -21,7 +21,7 @@ class sram_1bank_nomux_wmask_sparecols_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         if OPTS.tech_name == "sky130":
diff --git a/compiler/tests/20_sram_1bank_nomux_wmask_test.py b/compiler/tests/20_sram_1bank_nomux_wmask_test.py
index 5eb10212..10985ec3 100755
--- a/compiler/tests/20_sram_1bank_nomux_wmask_test.py
+++ b/compiler/tests/20_sram_1bank_nomux_wmask_test.py
@@ -20,7 +20,7 @@ class sram_1bank_nomux_wmask_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         if OPTS.tech_name == "sky130":
diff --git a/compiler/tests/20_sram_1bank_ring_test.py b/compiler/tests/20_sram_1bank_ring_test.py
index 5010a3de..af884bf2 100755
--- a/compiler/tests/20_sram_1bank_ring_test.py
+++ b/compiler/tests/20_sram_1bank_ring_test.py
@@ -20,7 +20,7 @@ class sram_1bank_nomux_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.supply_pin_type = "ring"
         from modules import sram_config
 
diff --git a/compiler/tests/20_sram_2bank_test.py b/compiler/tests/20_sram_2bank_test.py
index e2d144bf..7914be7b 100755
--- a/compiler/tests/20_sram_2bank_test.py
+++ b/compiler/tests/20_sram_2bank_test.py
@@ -21,7 +21,7 @@ class sram_2bank_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
         c = sram_config(word_size=16,
                         num_words=32,
diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py
index a5677a13..e5fdbdb9 100755
--- a/compiler/tests/21_hspice_delay_test.py
+++ b/compiler/tests/21_hspice_delay_test.py
@@ -20,7 +20,7 @@ class timing_sram_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.spice_name="hspice"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
diff --git a/compiler/tests/21_hspice_setuphold_test.py b/compiler/tests/21_hspice_setuphold_test.py
index 0ebcb167..dfd5ed68 100755
--- a/compiler/tests/21_hspice_setuphold_test.py
+++ b/compiler/tests/21_hspice_setuphold_test.py
@@ -19,7 +19,7 @@ class timing_setup_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.spice_name="hspice"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
diff --git a/compiler/tests/21_model_delay_test.py b/compiler/tests/21_model_delay_test.py
index 16924f0b..e606d2fd 100755
--- a/compiler/tests/21_model_delay_test.py
+++ b/compiler/tests/21_model_delay_test.py
@@ -21,7 +21,7 @@ class model_delay_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
 
diff --git a/compiler/tests/21_ngspice_delay_extra_rows_test.py b/compiler/tests/21_ngspice_delay_extra_rows_test.py
index 3935ac3d..343373d1 100755
--- a/compiler/tests/21_ngspice_delay_extra_rows_test.py
+++ b/compiler/tests/21_ngspice_delay_extra_rows_test.py
@@ -19,7 +19,7 @@ class timing_sram_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.spice_name="ngspice"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
diff --git a/compiler/tests/21_ngspice_delay_global_test.py b/compiler/tests/21_ngspice_delay_global_test.py
index 94ed2aba..9930cda4 100755
--- a/compiler/tests/21_ngspice_delay_global_test.py
+++ b/compiler/tests/21_ngspice_delay_global_test.py
@@ -21,7 +21,7 @@ class timing_sram_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.spice_name="ngspice"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py
index 28db8511..89561d23 100755
--- a/compiler/tests/21_ngspice_delay_test.py
+++ b/compiler/tests/21_ngspice_delay_test.py
@@ -19,7 +19,7 @@ class timing_sram_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.spice_name="ngspice"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
diff --git a/compiler/tests/21_ngspice_setuphold_test.py b/compiler/tests/21_ngspice_setuphold_test.py
index 70adfaaa..b4e71626 100755
--- a/compiler/tests/21_ngspice_setuphold_test.py
+++ b/compiler/tests/21_ngspice_setuphold_test.py
@@ -18,7 +18,7 @@ class timing_setup_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.spice_name="ngspice"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
diff --git a/compiler/tests/21_regression_delay_test.py b/compiler/tests/21_regression_delay_test.py
index 94ece131..0955e6d3 100755
--- a/compiler/tests/21_regression_delay_test.py
+++ b/compiler/tests/21_regression_delay_test.py
@@ -21,7 +21,7 @@ class regression_model_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
 
diff --git a/compiler/tests/21_xyce_delay_test.py b/compiler/tests/21_xyce_delay_test.py
index 705f432e..6fae1d9c 100755
--- a/compiler/tests/21_xyce_delay_test.py
+++ b/compiler/tests/21_xyce_delay_test.py
@@ -20,7 +20,7 @@ class timing_sram_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.spice_name="xyce"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
diff --git a/compiler/tests/21_xyce_setuphold_test.py b/compiler/tests/21_xyce_setuphold_test.py
index c2962c48..5cc212cf 100755
--- a/compiler/tests/21_xyce_setuphold_test.py
+++ b/compiler/tests/21_xyce_setuphold_test.py
@@ -18,7 +18,7 @@ class timing_setup_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.spice_name="Xyce"
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
diff --git a/compiler/tests/22_psram_1bank_2mux_func_test.py b/compiler/tests/22_psram_1bank_2mux_func_test.py
index f1d3707f..d44481ba 100755
--- a/compiler/tests/22_psram_1bank_2mux_func_test.py
+++ b/compiler/tests/22_psram_1bank_2mux_func_test.py
@@ -20,7 +20,7 @@ class psram_1bank_2mux_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/22_psram_1bank_4mux_func_test.py b/compiler/tests/22_psram_1bank_4mux_func_test.py
index 1e504625..084ccf95 100755
--- a/compiler/tests/22_psram_1bank_4mux_func_test.py
+++ b/compiler/tests/22_psram_1bank_4mux_func_test.py
@@ -21,7 +21,7 @@ class psram_1bank_4mux_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/22_psram_1bank_8mux_func_test.py b/compiler/tests/22_psram_1bank_8mux_func_test.py
index c2587221..a0151999 100755
--- a/compiler/tests/22_psram_1bank_8mux_func_test.py
+++ b/compiler/tests/22_psram_1bank_8mux_func_test.py
@@ -21,7 +21,7 @@ class psram_1bank_8mux_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/22_psram_1bank_nomux_func_test.py b/compiler/tests/22_psram_1bank_nomux_func_test.py
index 95fcdb14..70b8a0d6 100755
--- a/compiler/tests/22_psram_1bank_nomux_func_test.py
+++ b/compiler/tests/22_psram_1bank_nomux_func_test.py
@@ -20,7 +20,7 @@ class psram_1bank_nomux_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/22_sram_1bank_2mux_func_test.py b/compiler/tests/22_sram_1bank_2mux_func_test.py
index 3aafb76a..6c8988d6 100755
--- a/compiler/tests/22_sram_1bank_2mux_func_test.py
+++ b/compiler/tests/22_sram_1bank_2mux_func_test.py
@@ -21,7 +21,7 @@ class sram_1bank_2mux_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/22_sram_1bank_2mux_global_func_test.py b/compiler/tests/22_sram_1bank_2mux_global_func_test.py
index 4b3b3927..3e8b16ab 100755
--- a/compiler/tests/22_sram_1bank_2mux_global_func_test.py
+++ b/compiler/tests/22_sram_1bank_2mux_global_func_test.py
@@ -21,7 +21,7 @@ class sram_1bank_2mux_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py b/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py
index 20570a6c..3212a613 100755
--- a/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py
+++ b/compiler/tests/22_sram_1bank_2mux_sparecols_func_test.py
@@ -21,7 +21,7 @@ class sram_1bank_2mux_sparecols_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/22_sram_1bank_4mux_func_test.py b/compiler/tests/22_sram_1bank_4mux_func_test.py
index f2bee002..9579377a 100755
--- a/compiler/tests/22_sram_1bank_4mux_func_test.py
+++ b/compiler/tests/22_sram_1bank_4mux_func_test.py
@@ -21,7 +21,7 @@ class sram_1bank_4mux_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/22_sram_1bank_8mux_func_test.py b/compiler/tests/22_sram_1bank_8mux_func_test.py
index 61758281..8a9dbfdd 100755
--- a/compiler/tests/22_sram_1bank_8mux_func_test.py
+++ b/compiler/tests/22_sram_1bank_8mux_func_test.py
@@ -21,7 +21,7 @@ class sram_1bank_8mux_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py b/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py
index 76116485..182d700c 100755
--- a/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py
+++ b/compiler/tests/22_sram_1bank_nomux_1rw_1r_func_test.py
@@ -20,7 +20,7 @@ class psram_1bank_nomux_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/22_sram_1bank_nomux_func_test.py b/compiler/tests/22_sram_1bank_nomux_func_test.py
index 5617b3fe..c26237a8 100755
--- a/compiler/tests/22_sram_1bank_nomux_func_test.py
+++ b/compiler/tests/22_sram_1bank_nomux_func_test.py
@@ -21,7 +21,7 @@ class sram_1bank_nomux_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py b/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py
index 5b3e0908..1dd9c97f 100755
--- a/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py
+++ b/compiler/tests/22_sram_1bank_nomux_sparecols_func_test.py
@@ -21,7 +21,7 @@ class sram_1bank_nomux_sparecols_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py b/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py
index 09b77170..aba82832 100755
--- a/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py
+++ b/compiler/tests/22_sram_1bank_wmask_1rw_1r_func_test.py
@@ -20,7 +20,7 @@ class sram_wmask_1w_1r_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/22_sram_wmask_func_test.py b/compiler/tests/22_sram_wmask_func_test.py
index 570b515e..b5c68910 100755
--- a/compiler/tests/22_sram_wmask_func_test.py
+++ b/compiler/tests/22_sram_wmask_func_test.py
@@ -21,7 +21,7 @@ class sram_wmask_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/23_lib_sram_linear_regression_test.py b/compiler/tests/23_lib_sram_linear_regression_test.py
index 642c3b51..73c28d5b 100755
--- a/compiler/tests/23_lib_sram_linear_regression_test.py
+++ b/compiler/tests/23_lib_sram_linear_regression_test.py
@@ -19,7 +19,7 @@ class lib_sram_linear_regression_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.nominal_corner_only = False
         OPTS.netlist_only = True
         OPTS.model_name = "linear_regression"
diff --git a/compiler/tests/23_lib_sram_model_corners_test.py b/compiler/tests/23_lib_sram_model_corners_test.py
index 7a46aec5..7cc01d50 100755
--- a/compiler/tests/23_lib_sram_model_corners_test.py
+++ b/compiler/tests/23_lib_sram_model_corners_test.py
@@ -19,7 +19,7 @@ class lib_model_corners_lib_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.nominal_corner_only = False
         OPTS.netlist_only = True
 
diff --git a/compiler/tests/23_lib_sram_model_test.py b/compiler/tests/23_lib_sram_model_test.py
index ec918b00..f70d050b 100755
--- a/compiler/tests/23_lib_sram_model_test.py
+++ b/compiler/tests/23_lib_sram_model_test.py
@@ -19,7 +19,7 @@ class lib_sram_model_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.nominal_corner_only = False
         OPTS.netlist_only = True
 
diff --git a/compiler/tests/23_lib_sram_prune_test.py b/compiler/tests/23_lib_sram_prune_test.py
index b509a1b9..8b93b0d4 100755
--- a/compiler/tests/23_lib_sram_prune_test.py
+++ b/compiler/tests/23_lib_sram_prune_test.py
@@ -19,7 +19,7 @@ class lib_sram_prune_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = True
diff --git a/compiler/tests/23_lib_sram_test.py b/compiler/tests/23_lib_sram_test.py
index 34397ada..90cc3ed8 100755
--- a/compiler/tests/23_lib_sram_test.py
+++ b/compiler/tests/23_lib_sram_test.py
@@ -18,7 +18,7 @@ class lib_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
 
diff --git a/compiler/tests/24_lef_sram_test.py b/compiler/tests/24_lef_sram_test.py
index 675daed8..5da40095 100755
--- a/compiler/tests/24_lef_sram_test.py
+++ b/compiler/tests/24_lef_sram_test.py
@@ -20,7 +20,7 @@ class lef_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.route_supplies=False
         OPTS.check_lvsdrc=False
         from modules import sram
diff --git a/compiler/tests/25_verilog_multibank_test.py b/compiler/tests/25_verilog_multibank_test.py
index 91fb04ae..5f529aa4 100755
--- a/compiler/tests/25_verilog_multibank_test.py
+++ b/compiler/tests/25_verilog_multibank_test.py
@@ -19,7 +19,7 @@ class multibank_verilog_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.route_supplies=False
         OPTS.check_lvsdrc=False
         OPTS.netlist_only=True
diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py
index be2528b6..9d056a8e 100755
--- a/compiler/tests/25_verilog_sram_test.py
+++ b/compiler/tests/25_verilog_sram_test.py
@@ -19,7 +19,7 @@ class verilog_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.route_supplies=False
         OPTS.check_lvsdrc=False
         OPTS.netlist_only=True
diff --git a/compiler/tests/26_hspice_pex_pinv_test.py b/compiler/tests/26_hspice_pex_pinv_test.py
index 7dbd56a6..5d1f4b0e 100755
--- a/compiler/tests/26_hspice_pex_pinv_test.py
+++ b/compiler/tests/26_hspice_pex_pinv_test.py
@@ -22,7 +22,7 @@ class hspice_pex_pinv_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         import pinv
 
         # load the hspice
diff --git a/compiler/tests/26_ngspice_pex_pinv_test.py b/compiler/tests/26_ngspice_pex_pinv_test.py
index 31a6d5ae..c4d77bba 100755
--- a/compiler/tests/26_ngspice_pex_pinv_test.py
+++ b/compiler/tests/26_ngspice_pex_pinv_test.py
@@ -20,7 +20,7 @@ import debug
 class ngspice_pex_pinv_test(openram_test):
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         import pinv
 
         # load the ngspice
diff --git a/compiler/tests/26_sram_pex_test.py b/compiler/tests/26_sram_pex_test.py
index c8b101cb..13fa3b8b 100755
--- a/compiler/tests/26_sram_pex_test.py
+++ b/compiler/tests/26_sram_pex_test.py
@@ -21,7 +21,7 @@ class sram_pex_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.use_pex = True
 
diff --git a/compiler/tests/30_openram_back_end_test.py b/compiler/tests/30_openram_back_end_test.py
index 5519f42e..b23a20d9 100755
--- a/compiler/tests/30_openram_back_end_test.py
+++ b/compiler/tests/30_openram_back_end_test.py
@@ -21,7 +21,7 @@ class openram_back_end_test(openram_test):
     def runTest(self):
         OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME"))
         config_file = "{}/tests/configs/config_back_end".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing top-level back-end sram_compiler.py with 2-bit, 16 word SRAM.")
         out_file = "testsram"
diff --git a/compiler/tests/30_openram_front_end_test.py b/compiler/tests/30_openram_front_end_test.py
index 928ac74e..3202aa03 100755
--- a/compiler/tests/30_openram_front_end_test.py
+++ b/compiler/tests/30_openram_front_end_test.py
@@ -21,7 +21,7 @@ class openram_front_end_test(openram_test):
     def runTest(self):
         OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME"))
         config_file = "{}/tests/configs/config_front_end".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
 
         debug.info(1, "Testing top-level front-end sram_compiler.py with 2-bit, 16 word SRAM.")
         out_file = "testsram"
diff --git a/compiler/tests/50_riscv_1k_1rw1r_func_test.py b/compiler/tests/50_riscv_1k_1rw1r_func_test.py
index 2b770111..bf8744fa 100755
--- a/compiler/tests/50_riscv_1k_1rw1r_func_test.py
+++ b/compiler/tests/50_riscv_1k_1rw1r_func_test.py
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/50_riscv_1k_1rw_func_test.py b/compiler/tests/50_riscv_1k_1rw_func_test.py
index 9623f4af..4af2fd99 100755
--- a/compiler/tests/50_riscv_1k_1rw_func_test.py
+++ b/compiler/tests/50_riscv_1k_1rw_func_test.py
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/50_riscv_1rw1r_func_test.py b/compiler/tests/50_riscv_1rw1r_func_test.py
index 4b864193..91ea6716 100755
--- a/compiler/tests/50_riscv_1rw1r_func_test.py
+++ b/compiler/tests/50_riscv_1rw1r_func_test.py
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/50_riscv_1rw1r_phys_test.py b/compiler/tests/50_riscv_1rw1r_phys_test.py
index 47774828..3236d824 100755
--- a/compiler/tests/50_riscv_1rw1r_phys_test.py
+++ b/compiler/tests/50_riscv_1rw1r_phys_test.py
@@ -21,7 +21,7 @@ class riscv_phys_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         OPTS.num_rw_ports = 1
diff --git a/compiler/tests/50_riscv_1rw_func_test.py b/compiler/tests/50_riscv_1rw_func_test.py
index ee157a44..248757b5 100755
--- a/compiler/tests/50_riscv_1rw_func_test.py
+++ b/compiler/tests/50_riscv_1rw_func_test.py
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/50_riscv_1rw_phys_test.py b/compiler/tests/50_riscv_1rw_phys_test.py
index c4e574c1..9e8a5b93 100755
--- a/compiler/tests/50_riscv_1rw_phys_test.py
+++ b/compiler/tests/50_riscv_1rw_phys_test.py
@@ -21,7 +21,7 @@ class riscv_phys_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         from modules import sram_config
 
         if OPTS.tech_name == "sky130":
diff --git a/compiler/tests/50_riscv_2k_1rw1r_func_test.py b/compiler/tests/50_riscv_2k_1rw1r_func_test.py
index ffa7ca03..538f5f06 100755
--- a/compiler/tests/50_riscv_2k_1rw1r_func_test.py
+++ b/compiler/tests/50_riscv_2k_1rw1r_func_test.py
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/50_riscv_2k_1rw_func_test.py b/compiler/tests/50_riscv_2k_1rw_func_test.py
index a48a03c0..422de33f 100755
--- a/compiler/tests/50_riscv_2k_1rw_func_test.py
+++ b/compiler/tests/50_riscv_2k_1rw_func_test.py
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/50_riscv_4k_1rw1r_func_test.py b/compiler/tests/50_riscv_4k_1rw1r_func_test.py
index 431b5390..76817e24 100755
--- a/compiler/tests/50_riscv_4k_1rw1r_func_test.py
+++ b/compiler/tests/50_riscv_4k_1rw1r_func_test.py
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/50_riscv_4k_1rw_func_test.py b/compiler/tests/50_riscv_4k_1rw_func_test.py
index 45254ac4..911549c0 100755
--- a/compiler/tests/50_riscv_4k_1rw_func_test.py
+++ b/compiler/tests/50_riscv_4k_1rw_func_test.py
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/50_riscv_512b_1rw1r_func_test.py b/compiler/tests/50_riscv_512b_1rw1r_func_test.py
index 26682139..21854a24 100755
--- a/compiler/tests/50_riscv_512b_1rw1r_func_test.py
+++ b/compiler/tests/50_riscv_512b_1rw1r_func_test.py
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/50_riscv_512b_1rw_func_test.py b/compiler/tests/50_riscv_512b_1rw_func_test.py
index 0af228a9..b5101e49 100755
--- a/compiler/tests/50_riscv_512b_1rw_func_test.py
+++ b/compiler/tests/50_riscv_512b_1rw_func_test.py
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/50_riscv_8k_1rw1r_func_test.py b/compiler/tests/50_riscv_8k_1rw1r_func_test.py
index f2861bad..128b5615 100755
--- a/compiler/tests/50_riscv_8k_1rw1r_func_test.py
+++ b/compiler/tests/50_riscv_8k_1rw1r_func_test.py
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/compiler/tests/50_riscv_8k_1rw_func_test.py b/compiler/tests/50_riscv_8k_1rw_func_test.py
index 22db186e..a2696aca 100755
--- a/compiler/tests/50_riscv_8k_1rw_func_test.py
+++ b/compiler/tests/50_riscv_8k_1rw_func_test.py
@@ -21,7 +21,7 @@ class riscv_func_test(openram_test):
 
     def runTest(self):
         config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
-        globals.init_openram(config_file)
+        globals.init_openram(config_file, is_unit_test=True)
         OPTS.analytical_delay = False
         OPTS.netlist_only = True
         OPTS.trim_netlist = False
diff --git a/sram_compiler.py b/sram_compiler.py
index 2c0a8f62..1a2d42b9 100755
--- a/sram_compiler.py
+++ b/sram_compiler.py
@@ -46,7 +46,7 @@ if len(args) != 1:
 import debug
 
 # Parse config file and set up all the options
-openram.init_openram(config_file=args[0], is_unit_test=False)
+openram.init_openram(config_file=args[0])
 
 # Ensure that the right bitcell exists or use the parameterised one
 openram.setup_bitcell()