Move mem reg before usage for compatibility

compiler/base/verilog.py

@@ -94,12 +94,12 @@ class verilog:
 
         self.vf.write("\n")
 
+        # This is the memory array itself
+        self.vf.write("  reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];\n\n")
+
         for port in self.all_ports:
             self.register_inputs(port)
 
-        # This is the memory array itself
-        self.vf.write("reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];\n")
-
         for port in self.all_ports:
             if port in self.write_ports:
                 self.add_write_block(port)

compiler/tests/golden/sram_2_16_1_freepdk45.v

@@ -30,6 +30,8 @@ module sram_2_16_1_freepdk45(
   input [DATA_WIDTH-1:0]  din0;
   output [DATA_WIDTH-1:0] dout0;
 
+  reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
+
   reg  csb0_reg;
   reg  web0_reg;
   reg [ADDR_WIDTH-1:0]  addr0_reg;
@@ -50,7 +52,6 @@ module sram_2_16_1_freepdk45(
       $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);
   end
 
-reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
 
   // Memory Write Block Port 0
   // Write Operation : When web0 = 0, csb0 = 0

compiler/tests/golden/sram_2_16_1_scn4m_subm.v

@@ -30,6 +30,8 @@ module sram_2_16_1_scn4m_subm(
   input [DATA_WIDTH-1:0]  din0;
   output [DATA_WIDTH-1:0] dout0;
 
+  reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
+
   reg  csb0_reg;
   reg  web0_reg;
   reg [ADDR_WIDTH-1:0]  addr0_reg;
@@ -50,7 +52,6 @@ module sram_2_16_1_scn4m_subm(
       $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);
   end
 
-reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
 
   // Memory Write Block Port 0
   // Write Operation : When web0 = 0, csb0 = 0