diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py
index 9cfd7d7c..414b4491 100644
--- a/compiler/base/verilog.py
+++ b/compiler/base/verilog.py
@@ -94,12 +94,12 @@ class verilog:
 
         self.vf.write("\n")
 
+        # This is the memory array itself
+        self.vf.write("  reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];\n\n")
+
         for port in self.all_ports:
             self.register_inputs(port)
 
-        # This is the memory array itself
-        self.vf.write("reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];\n")
-
         for port in self.all_ports:
             if port in self.write_ports:
                 self.add_write_block(port)
@@ -162,7 +162,7 @@ class verilog:
         if port in self.read_ports:
             self.vf.write("    #(T_HOLD) dout{0} = {1}'bx;\n".format(port, self.word_size))
         if port in self.readwrite_ports:
-            self.vf.write("    if ( !csb{0}_reg && web{0}_reg && VERBOSE ) \n".format(port))
+            self.vf.write("    if ( !csb{0}_reg && web{0}_reg && VERBOSE )\n".format(port))
             self.vf.write("      $display($time,\" Reading %m addr{0}=%b dout{0}=%b\",addr{0}_reg,mem[addr{0}_reg]);\n".format(port))
         elif port in self.read_ports:
             self.vf.write("    if ( !csb{0}_reg && VERBOSE ) \n".format(port))
diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45.v b/compiler/tests/golden/sram_2_16_1_freepdk45.v
index 859d1cc6..da4625a9 100644
--- a/compiler/tests/golden/sram_2_16_1_freepdk45.v
+++ b/compiler/tests/golden/sram_2_16_1_freepdk45.v
@@ -30,6 +30,8 @@ module sram_2_16_1_freepdk45(
   input [DATA_WIDTH-1:0]  din0;
   output [DATA_WIDTH-1:0] dout0;
 
+  reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
+
   reg  csb0_reg;
   reg  web0_reg;
   reg [ADDR_WIDTH-1:0]  addr0_reg;
@@ -44,13 +46,12 @@ module sram_2_16_1_freepdk45(
     addr0_reg = addr0;
     din0_reg = din0;
     #(T_HOLD) dout0 = 2'bx;
-    if ( !csb0_reg && web0_reg && VERBOSE ) 
+    if ( !csb0_reg && web0_reg && VERBOSE )
       $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
     if ( !csb0_reg && !web0_reg && VERBOSE )
       $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);
   end
 
-reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
 
   // Memory Write Block Port 0
   // Write Operation : When web0 = 0, csb0 = 0
diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm.v b/compiler/tests/golden/sram_2_16_1_scn4m_subm.v
index ce3714b2..0d25d63b 100644
--- a/compiler/tests/golden/sram_2_16_1_scn4m_subm.v
+++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm.v
@@ -30,6 +30,8 @@ module sram_2_16_1_scn4m_subm(
   input [DATA_WIDTH-1:0]  din0;
   output [DATA_WIDTH-1:0] dout0;
 
+  reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
+
   reg  csb0_reg;
   reg  web0_reg;
   reg [ADDR_WIDTH-1:0]  addr0_reg;
@@ -44,13 +46,12 @@ module sram_2_16_1_scn4m_subm(
     addr0_reg = addr0;
     din0_reg = din0;
     #(T_HOLD) dout0 = 2'bx;
-    if ( !csb0_reg && web0_reg && VERBOSE ) 
+    if ( !csb0_reg && web0_reg && VERBOSE )
       $display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
     if ( !csb0_reg && !web0_reg && VERBOSE )
       $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);
   end
 
-reg [DATA_WIDTH-1:0]    mem [0:RAM_DEPTH-1];
 
   // Memory Write Block Port 0
   // Write Operation : When web0 = 0, csb0 = 0