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Move mem reg before usage for compatibility

This commit is contained in:
mrg 2021-10-13 09:46:02 -07:00
parent ccab2f8064
commit e6a009312e
3 changed files with 10 additions and 8 deletions
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6
compiler/base/verilog.py
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@ -94,12 +94,12 @@ class verilog:
self.vf.write("\n") self.vf.write("\n")
# This is the memory array itself
self.vf.write(" reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];\n\n")
for port in self.all_ports: for port in self.all_ports:
self.register_inputs(port) self.register_inputs(port)
# This is the memory array itself
self.vf.write("reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];\n")
for port in self.all_ports: for port in self.all_ports:
if port in self.write_ports: if port in self.write_ports:
self.add_write_block(port) self.add_write_block(port)

3
compiler/tests/golden/sram_2_16_1_freepdk45.v
View File

@ -30,6 +30,8 @@ module sram_2_16_1_freepdk45(
input [DATA_WIDTH-1:0] din0; input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0; output [DATA_WIDTH-1:0] dout0;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
reg csb0_reg; reg csb0_reg;
reg web0_reg; reg web0_reg;
reg [ADDR_WIDTH-1:0] addr0_reg; reg [ADDR_WIDTH-1:0] addr0_reg;
@ -50,7 +52,6 @@ module sram_2_16_1_freepdk45(
$display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg); $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);
end end
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
// Memory Write Block Port 0 // Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0 // Write Operation : When web0 = 0, csb0 = 0

3
compiler/tests/golden/sram_2_16_1_scn4m_subm.v
View File

@ -30,6 +30,8 @@ module sram_2_16_1_scn4m_subm(
input [DATA_WIDTH-1:0] din0; input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0; output [DATA_WIDTH-1:0] dout0;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
reg csb0_reg; reg csb0_reg;
reg web0_reg; reg web0_reg;
reg [ADDR_WIDTH-1:0] addr0_reg; reg [ADDR_WIDTH-1:0] addr0_reg;
@ -50,7 +52,6 @@ module sram_2_16_1_scn4m_subm(
$display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg); $display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);
end end
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
// Memory Write Block Port 0 // Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0 // Write Operation : When web0 = 0, csb0 = 0