adding 6T transistor size parameters to tech files for use in pbitcell.

2026-08-29 01:24:39 +02:00 · 2018-10-17 07:28:56 -07:00
parent 69a1560186
commit e60deddfea
4 changed files with 33 additions and 13 deletions
@@ -71,6 +71,10 @@ parameter={}
 parameter["min_tx_size"] = 0.09
 parameter["beta"] = 3

+parameter["6T_inv_nmos_size"] = 0.205
+parameter["6T_inv_pmos_size"] = 0.09
+parameter["6T_access_size"] = 0.135
+
 drclvs_home=os.environ.get("DRCLVS_HOME")
 drc={}
 #grid size