From e60deddfeabc23dca242f8d69a7559c1ce75fdab Mon Sep 17 00:00:00 2001
From: Michael Timothy Grimes <mtgrimes@mada0.SOE.UCSC.EDU>
Date: Wed, 17 Oct 2018 07:28:56 -0700
Subject: [PATCH] adding 6T transistor size parameters to tech files for use in
 pbitcell.

---
 compiler/pgates/pbitcell.py         | 34 ++++++++++++++++++-----------
 technology/freepdk45/tech/tech.py   |  4 ++++
 technology/scn3me_subm/tech/tech.py |  4 ++++
 technology/scn4m_subm/tech/tech.py  |  4 ++++
 4 files changed, 33 insertions(+), 13 deletions(-)

diff --git a/compiler/pgates/pbitcell.py b/compiler/pgates/pbitcell.py
index ee5128af..b02ceee1 100644
--- a/compiler/pgates/pbitcell.py
+++ b/compiler/pgates/pbitcell.py
@@ -142,19 +142,19 @@ class pbitcell(design.design):
         """
         # if there are any read/write ports, then the inverter nmos is sized based the number of read/write ports
         if(self.num_rw_ports > 0):
-            inverter_nmos_width = self.num_rw_ports*3*parameter["min_tx_size"]
-            inverter_pmos_width = parameter["min_tx_size"]
-            readwrite_nmos_width = 1.5*parameter["min_tx_size"]
-            write_nmos_width = parameter["min_tx_size"]
-            read_nmos_width = 2*parameter["min_tx_size"]
+            inverter_nmos_width = self.num_rw_ports*parameter["6T_inv_nmos_size"]
+            inverter_pmos_width = parameter["6T_inv_pmos_size"]
+            readwrite_nmos_width = parameter["6T_access_size"]
+            write_nmos_width = parameter["6T_access_size"]
+            read_nmos_width = 2*parameter["6T_inv_pmos_size"]
         
         # if there are no read/write ports, then the inverter nmos is statically sized for the dual port case
         else:
-            inverter_nmos_width = 2*parameter["min_tx_size"]
-            inverter_pmos_width = parameter["min_tx_size"]
-            readwrite_nmos_width = 1.5*parameter["min_tx_size"]
-            write_nmos_width = parameter["min_tx_size"]
-            read_nmos_width = 2*parameter["min_tx_size"]
+            inverter_nmos_width = 2*parameter["6T_inv_pmos_size"]
+            inverter_pmos_width = parameter["6T_inv_pmos_size"]
+            readwrite_nmos_width = parameter["6T_access_size"]
+            write_nmos_width = parameter["6T_access_size"]
+            read_nmos_width = 2*parameter["6T_inv_pmos_size"]
     
         # create ptx for inverter transistors
         self.inverter_nmos = ptx(width=inverter_nmos_width,
@@ -206,9 +206,17 @@ class pbitcell(design.design):
         
         # calculations related to inverter connections
         inverter_pmos_contact_extension = 0.5*(self.inverter_pmos.active_contact.height - self.inverter_pmos.active_height)
-        self.inverter_gap = self.poly_to_active + self.poly_to_polycontact + 2*contact.poly.width + self.m1_space + inverter_pmos_contact_extension
-        self.cross_couple_lower_ypos = self.inverter_nmos_ypos + self.inverter_nmos.active_height + self.poly_to_active + 0.5*contact.poly.width
-        self.cross_couple_upper_ypos = self.inverter_nmos_ypos + self.inverter_nmos.active_height + self.poly_to_active + self.poly_to_polycontact + 1.5*contact.poly.width
+        inverter_nmos_contact_extension = 0.5*(self.inverter_nmos.active_contact.height - self.inverter_nmos.active_height)
+        self.inverter_gap = max(self.poly_to_active, self.m1_space + inverter_nmos_contact_extension) \
+                            + self.poly_to_polycontact + 2*contact.poly.width \
+                            + self.m1_space + inverter_pmos_contact_extension
+        self.cross_couple_lower_ypos = self.inverter_nmos_ypos + self.inverter_nmos.active_height \
+                                       + max(self.poly_to_active, self.m1_space + inverter_nmos_contact_extension) \
+                                       + 0.5*contact.poly.width
+        self.cross_couple_upper_ypos = self.inverter_nmos_ypos + self.inverter_nmos.active_height \
+                                       + max(self.poly_to_active, self.m1_space + inverter_nmos_contact_extension) \
+                                       + self.poly_to_polycontact \
+                                       + 1.5*contact.poly.width
         
         # spacing between wordlines (and gnd)
         self.rowline_spacing = self.m1_space + contact.m1m2.width
diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py
index 74bef19c..6c407ec0 100644
--- a/technology/freepdk45/tech/tech.py
+++ b/technology/freepdk45/tech/tech.py
@@ -71,6 +71,10 @@ parameter={}
 parameter["min_tx_size"] = 0.09
 parameter["beta"] = 3
 
+parameter["6T_inv_nmos_size"] = 0.205
+parameter["6T_inv_pmos_size"] = 0.09
+parameter["6T_access_size"] = 0.135
+
 drclvs_home=os.environ.get("DRCLVS_HOME")
 drc={}
 #grid size
diff --git a/technology/scn3me_subm/tech/tech.py b/technology/scn3me_subm/tech/tech.py
index e6bf6da1..c24d532a 100755
--- a/technology/scn3me_subm/tech/tech.py
+++ b/technology/scn3me_subm/tech/tech.py
@@ -57,6 +57,10 @@ parameter={}
 parameter["min_tx_size"] = 4*_lambda_
 parameter["beta"] = 2 
 
+parameter["6T_inv_nmos_size"] = 8*_lambda_
+parameter["6T_inv_pmos_size"] = 3*_lambda_
+parameter["6T_access_size"] = 4*_lambda_
+
 drclvs_home=os.environ.get("DRCLVS_HOME")
 
 drc={}
diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py
index fc7440e1..68f70bcc 100755
--- a/technology/scn4m_subm/tech/tech.py
+++ b/technology/scn4m_subm/tech/tech.py
@@ -59,6 +59,10 @@ parameter={}
 parameter["min_tx_size"] = 4*_lambda_
 parameter["beta"] = 2 
 
+parameter["6T_inv_nmos_size"] = 8*_lambda_
+parameter["6T_inv_pmos_size"] = 3*_lambda_
+parameter["6T_access_size"] = 4*_lambda_
+
 drclvs_home=os.environ.get("DRCLVS_HOME")
 
 drc={}