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Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass.

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Hunter Nichols
2018-10-30 22:19:26 -07:00
parent 3bb8aa7e55
commit e5dcf5d5b1
9 changed files with 40 additions and 18 deletions
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technology/scn4m_subm/tech/tech.py
+1 -1
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@@ -240,7 +240,7 @@ spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"
#spice stimulus related variables
spice["feasible_period"] = 5 # estimated feasible period in ns
spice["feasible_period"] = 5 # estimated feasible period in ns
spice["supply_voltages"] = [4.5, 5.0, 5.5] # Supply voltage corners in [Volts]
spice["nom_supply_voltage"] = 5.0 # Nominal supply voltage in [Volts]
spice["rise_time"] = 0.05 # rise time in [Nano-seconds]