diff --git a/compiler/sram_1bank.py b/compiler/sram_1bank.py
index e43dac72..9324d7d0 100644
--- a/compiler/sram_1bank.py
+++ b/compiler/sram_1bank.py
@@ -10,6 +10,7 @@ from globals import OPTS, print_time
 
 from sram_base import sram_base
 from bank import bank
+from contact import m2m3
 from dff_buf_array import dff_buf_array
 from dff_array import dff_array
 
@@ -216,6 +217,9 @@ class sram_1bank(sram_base):
                 data_dff_clk_pin = self.data_dff_insts[port].get_pin("clk")
                 data_dff_clk_pos = data_dff_clk_pin.center()
                 mid_pos = vector(clk_steiner_pos.x, data_dff_clk_pos.y)
+                # In some designs, the steiner via will be too close to the mid_pos via
+                # so make the wire as wide as the contacts
+                self.add_path("metal2",[mid_pos, clk_steiner_pos], width=max(m2m3.width,m2m3.height))
                 self.add_wire(("metal3","via2","metal2"),[data_dff_clk_pos, mid_pos, clk_steiner_pos])