Update property settings with getters/setters

compiler/bitcells/bitcell_1port.py

@@ -19,7 +19,7 @@ class bitcell_1port(bitcell_base.bitcell_base):
     """
 
     def __init__(self, name):
-        super().__init__(name, props.bitcell_1port)
+        super().__init__(name, prop=props.bitcell_1port)
         debug.info(2, "Create bitcell")
 
     def get_all_wl_names(self):

compiler/bitcells/bitcell_2port.py

@@ -19,7 +19,7 @@ class bitcell_2port(bitcell_base.bitcell_base):
     """
 
     def __init__(self, name):
-        super().__init__(name, props.bitcell_2port)
+        super().__init__(name, prop=props.bitcell_2port)
         debug.info(2, "Create bitcell with 2 ports")
 
         self.bl_names = [props.bitcell_2port.pin.bl0, props.bitcell_2port.pin.bl1]

compiler/bitcells/bitcell_base.py

@@ -8,34 +8,25 @@
 
 import debug
 import design
-import utils
 from globals import OPTS
 import logical_effort
-from tech import GDS, parameter, drc, layer
+from tech import parameter, drc, layer
 
 
 class bitcell_base(design.design):
     """
     Base bitcell parameters to be over-riden.
     """
-    def __init__(self, name, prop=None):
-        design.design.__init__(self, name)
+    def __init__(self, name, cell_name=None, prop=None):
+        design.design.__init__(self, name, cell_name, prop)
 
+        # Set the bitcell specific properties
         if prop:
-            self.pins = prop.port_names
-            self.add_pin_types(prop.port_types)
             self.storage_nets = prop.storage_nets
             self.nets_match = self.do_nets_exist(prop.storage_nets)
             self.mirror = prop.mirror
             self.end_caps = prop.end_caps
         
-            (self.width, self.height) = utils.get_libcell_size(self.cell_name,
-                                                               GDS["unit"],
-                                                               layer[prop.boundary_layer])
-            self.pin_map = utils.get_libcell_pins(self.pins,
-                                                  self.cell_name,
-                                                  GDS["unit"])
-
     def get_stage_effort(self, load):
         parasitic_delay = 1
         # This accounts for bitline being drained

compiler/bitcells/col_cap_bitcell_2port.py

@@ -10,21 +10,13 @@ from tech import cell_properties as props
 import bitcell_base
 
 
-class col_cap_bitcell_1rw_1r(bitcell_base.bitcell_base):
+class col_cap_bitcell_2port(bitcell_base.bitcell_base):
     """
     Column end cap cell. 
     """
 
-    pin_names = [props.bitcell.cell_1rw1r.pin.bl0,
-                 props.bitcell.cell_1rw1r.pin.br0,
-                 props.bitcell.cell_1rw1r.pin.bl1,
-                 props.bitcell.cell_1rw1r.pin.br1,
-                 props.bitcell.cell_1rw1r.pin.vdd]
-    type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT",
-                 "POWER", "GROUND"]
-
     def __init__(self, name="col_cap_cell_1rw_1r"):
-        bitcell_base.bitcell_base.__init__(self, name)
-        debug.info(2, "Create col_cap bitcell 1rw+1r object")
+        bitcell_base.bitcell_base.__init__(self, name, prop=props.bitcell_2port)
+        debug.info(2, "Create col_cap bitcell 2 port object")
 
         self.no_instances = True

compiler/bitcells/dummy_bitcell_1port.py

@@ -18,7 +18,7 @@ class dummy_bitcell_1port(bitcell_base.bitcell_base):
     library.
     """
     def __init__(self, name):
-        super().__init__(name, props.bitcell_1port)
+        super().__init__(name, prop=props.bitcell_1port)
         debug.info(2, "Create dummy bitcell")
 
 

compiler/bitcells/dummy_bitcell_2port.py

@@ -18,7 +18,7 @@ class dummy_bitcell_2port(bitcell_base.bitcell_base):
     the technology library. """
 
     def __init__(self, name):
-        super().__init__(name, props.bitcell_2port)
+        super().__init__(name, prop=props.bitcell_2port)
         debug.info(2, "Create dummy bitcell 2 port object")
 
 

compiler/bitcells/replica_bitcell_1port.py

@@ -20,7 +20,7 @@ class replica_bitcell_1port(bitcell_base.bitcell_base):
     the technology library. """
 
     def __init__(self, name):
-        super().__init__(name, props.bitcell_1port)
+        super().__init__(name, prop=props.bitcell_1port)
         debug.info(2, "Create replica bitcell object")
 
     def get_stage_effort(self, load):

compiler/bitcells/replica_bitcell_2port.py

@@ -20,7 +20,7 @@ class replica_bitcell_2port(bitcell_base.bitcell_base):
     the technology library. """
 
     def __init__(self, name):
-        super().__init__(name, props.bitcell_2port)
+        super().__init__(name, prop=props.bitcell_2port)
         debug.info(2, "Create replica bitcell 2 port object")
 
     def get_stage_effort(self, load):

compiler/bitcells/row_cap_bitcell_2port.py

@@ -10,18 +10,13 @@ from tech import cell_properties as props
 import bitcell_base
 
 
-class row_cap_bitcell_1rw_1r(bitcell_base.bitcell_base):
+class row_cap_bitcell_2port(bitcell_base.bitcell_base):
     """
     Row end cap cell. 
     """
 
-    pin_names = [props.bitcell.cell_1rw1r.pin.wl0,
-                 props.bitcell.cell_1rw1r.pin.wl1,
-                 props.bitcell.cell_1rw1r.pin.gnd]
-    type_list = ["INPUT", "INPUT", "GROUND"]
-
     def __init__(self, name="row_cap_cell_1rw_1r"):
-        bitcell_base.bitcell_base.__init__(self, name)
+        bitcell_base.bitcell_base.__init__(self, name, prop=props.bitcell_2port)
         debug.info(2, "Create row_cap bitcell 1rw+1r object")
 
         self.no_instances = True