Update property settings with getters/setters

compiler/base/custom_cell_properties.py

@@ -18,16 +18,13 @@ class _cell:
         if not port_map:
             port_map = {x: x for x in port_order}
 
-        self.set_ports(port_order, port_map)
-
-    def set_ports(self,
-                  port_order,
-                  port_map):
         # Update mapping of names
         self._pins = _pins(port_map)
         self._port_order = port_order
+        
         # Update ordered name list
         self._port_names = [getattr(self._pins, x) for x in self._port_order]
+        
         # Update ordered type list
         self._port_types = [self._port_types_map[x] for x in port_order]
         
@@ -43,6 +40,29 @@ class _cell:
     def port_names(self):
         return self._port_names
 
+    @property
+    def port_order(self):
+        return self._port_order
+
+    @port_order.setter
+    def port_order(self, x):
+        self._port_order = x
+        # Update ordered name list in the new order
+        self._port_names = [getattr(self._pins, x) for x in self._port_order]
+        # Update ordered type list in the new order
+        self._port_types = [self._port_types_map[x] for x in self._port_order]
+
+    @property
+    def port_map(self):
+        return self._port_map
+    
+    @port_map.setter
+    def port_map(self, x):
+        self._port_map = x
+        self._pins = _pins(x)
+        # Update ordered name list to use the new names
+        self._port_names = [getattr(self._pins, x) for x in self._port_order]
+    
     @property
     def port_types(self):
         return self._port_types
@@ -50,7 +70,11 @@ class _cell:
     @property
     def boundary_layer(self):
         return self._boundary_layer
-    
+
+    @boundary_layer.setter
+    def boundary_layer(self, x):
+        self._boundary_layer = x
+        
     
 class _pins:
     def __init__(self, pin_dict):
@@ -116,13 +140,16 @@ class cell_properties():
 
         self._pgate = _pgate(add_implants=False)
 
+        self._inv_dec = _cell(["A", "Z", "vdd", "gnd"],
+                              ["INPUT", "OUTPUT", "POWER", "GROUND"])
+        
         self._nand2_dec = _cell(["A", "B", "Z", "vdd", "gnd"],
                                 ["INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"])
         
-        self._nand2_dec = _cell(["A", "B", "C", "Z", "vdd", "gnd"],
+        self._nand3_dec = _cell(["A", "B", "C", "Z", "vdd", "gnd"],
                                 ["INPUT", "INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"])
         
-        self._nand2_dec = _cell(["A", "B", "C", "D", "Z", "vdd", "gnd"],
+        self._nand4_dec = _cell(["A", "B", "C", "D", "Z", "vdd", "gnd"],
                                 ["INPUT", "INPUT", "INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"])
         
         self._dff = _cell(["D", "Q", "clk", "vdd", "gnd"],
@@ -152,6 +179,22 @@ class cell_properties():
     def pgate(self):
         return self._pgate
 
+    @property
+    def inv_dec(self):
+        return self._inv_dec
+
+    @property
+    def nand2_dec(self):
+        return self._nand2_dec
+    
+    @property
+    def nand3_dec(self):
+        return self._nand3_dec
+    
+    @property
+    def nand4_dec(self):
+        return self._nand4_dec
+    
     @property
     def dff(self):
         return self._dff

compiler/base/design.py

@@ -22,7 +22,7 @@ class design(hierarchy_design):
     some DRC/layer constants and analytical models for other modules to reuse.
     """
 
-    def __init__(self, name, cell_name=None):
+    def __init__(self, name, cell_name=None, prop=None):
         # This allows us to use different GDS/spice circuits for hard cells instead of the default ones
         # Except bitcell names are generated automatically by the globals.py setup_bitcells routines
         # depending on the number of ports.
@@ -32,25 +32,24 @@ class design(hierarchy_design):
             cell_name = name
         super().__init__(name, cell_name)
 
-        # This means it is a custom cell...
-        if hasattr(props, name):
-            prop = getattr(props, name)
-            if prop.hard_cell:
-                # The pins get added from the spice file
-                debug.check(prop.port_names == self.pins,
-                            "Custom cell pin names do not match spice file:\n{0} vs {1}".format(prop.port_names, self.pins))
-                self.add_pin_types(prop.port_types)
+        # This means it is a custom cell.
+        # It could have properties and not be a hard cell too (e.g. dff_buf)
+        if prop and prop.hard_cell:
+            # The pins get added from the spice file
+            debug.check(prop.port_names == self.pins,
+                        "Custom cell pin names do not match spice file:\n{0} vs {1}".format(prop.port_names, self.pins))
+            self.add_pin_types(prop.port_types)
             
-                (width, height) = utils.get_libcell_size(self.cell_name,
-                                                         GDS["unit"],
-                                                         layer[prop.boundary_layer])
+            (width, height) = utils.get_libcell_size(self.cell_name,
+                                                     GDS["unit"],
+                                                     layer[prop.boundary_layer])
 
-                self.pin_map = utils.get_libcell_pins(self.pins,
-                                                      self.cell_name,
-                                                      GDS["unit"])
+            self.pin_map = utils.get_libcell_pins(self.pins,
+                                                  self.cell_name,
+                                                  GDS["unit"])
 
-                self.width = width
-                self.height = height
+            self.width = width
+            self.height = height
 
         self.setup_multiport_constants()