mirror of https://github.com/VLSIDA/OpenRAM.git
Adjusted test values to account for recent changes.
This commit is contained in:
Hunter Nichols
parent
543e0a1b9a
commit
e3d003d410
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@ -51,35 +51,36 @@ class timing_sram_test(openram_test):
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data.update(port_data[0])
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if OPTS.tech_name == "freepdk45":
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golden_data = {'delay_hl': [0.2011],
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'delay_lh': [0.2011],
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'leakage_power': 0.002,
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'min_period': 0.41,
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'read0_power': [0.63604],
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'read1_power': [0.6120599999999999],
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'slew_hl': [0.07078999999999999],
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'slew_lh': [0.07078999999999999],
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'write0_power': [0.51742],
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'write1_power': [0.51095],
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'volt_bl': [0.2017],
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'volt_br': [1.0765],
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'delay_bl': [0.18114999999999998],
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'delay_br': [0.17763]}
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golden_data = {'delay_bl': [0.19683],
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'delay_br': [0.19474],
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'delay_hl': [0.20646],
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'delay_lh': [0.20646],
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'leakage_power': 0.0013155,
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'min_period': 0.43,
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'read0_power': [0.50758],
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'read1_power': [0.48225999999999997],
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'slew_hl': [0.045869],
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'slew_lh': [0.045869],
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'volt_bl': [0.6563],
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'volt_br': [1.117],
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'write0_power': [0.46124000000000004],
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'write1_power': [0.48225999999999997]}
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elif OPTS.tech_name == "scn4m_subm":
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golden_data = {'delay_hl': [1.3911],
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'delay_lh': [1.3911],
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'leakage_power': 0.0278488,
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'min_period': 2.812,
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'read0_power': [22.1183],
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'read1_power': [21.4388],
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'slew_hl': [0.6],
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'slew_lh': [0.6],
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'write0_power': [19.4103],
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'write1_power': [20.1167],
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'volt_bl': [3.1763],
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'volt_br': [5.5731],
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'delay_bl': [1.1133000000000002],
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'delay_br': [0.9958395]}
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golden_data = {'delay_bl': [1.1029],
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'delay_br': [0.9656455999999999],
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'delay_hl': [1.288],
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'delay_lh': [1.288],
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'leakage_power': 0.0273896,
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'min_period': 2.578,
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'read0_power': [16.9996],
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'read1_power': [16.2616],
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'slew_hl': [0.47891700000000004],
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'slew_lh': [0.47891700000000004],
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'volt_bl': [4.2155],
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'volt_br': [5.8142],
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'write0_power': [16.0656],
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'write1_power': [16.2616]}
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else:
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self.assertTrue(False) # other techs fail
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# Check if no too many or too few results
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@ -51,35 +51,36 @@ class timing_sram_test(openram_test):
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data.update(port_data[0])
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if OPTS.tech_name == "freepdk45":
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golden_data = {'delay_bl': [0.1840938],
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'delay_br': [0.1804373],
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'delay_hl': [0.2130831],
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'delay_lh': [0.2130831],
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'leakage_power': 0.001595639,
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'min_period': 0.527,
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'read0_power': [0.4852456],
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'read1_power': [0.46341889999999997],
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'slew_hl': [0.07351041999999999],
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'slew_lh': [0.07351041999999999],
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'volt_bl': [0.1954744],
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'volt_br': [1.058266],
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'write0_power': [0.4065201],
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'write1_power': [0.46341889999999997]}
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golden_data = {'delay_bl': [0.2003652],
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'delay_br': [0.198698],
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'delay_hl': [0.2108836],
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'delay_lh': [0.2108836],
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'leakage_power': 0.001564799,
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'min_period': 0.508,
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'read0_power': [0.43916689999999997],
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'read1_power': [0.4198608],
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'slew_hl': [0.0455126],
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'slew_lh': [0.0455126],
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'volt_bl': [0.6472883],
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'volt_br': [1.114024],
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'write0_power': [0.40681890000000004],
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'write1_power': [0.4198608]}
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elif OPTS.tech_name == "scn4m_subm":
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golden_data = {'delay_hl': [1.610911],
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'delay_lh': [1.610911],
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'leakage_power': 0.0023593859999999998,
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golden_data = {'delay_bl': [1.3937359999999999],
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'delay_br': [1.2596429999999998],
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'delay_hl': [1.5747600000000002],
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'delay_lh': [1.5747600000000002],
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'leakage_power': 0.00195795,
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'min_period': 3.281,
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'read0_power': [20.763569999999998],
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'read1_power': [20.32745],
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'slew_hl': [0.7986348999999999],
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'slew_lh': [0.7986348999999999],
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'write0_power': [17.58272],
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'write1_power': [18.523419999999998],
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'volt_bl': [3.1763],
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'volt_br': [5.5731],
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'delay_bl': [1.1133000000000002],
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'delay_br': [0.9958395]}
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'read0_power': [14.92874],
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'read1_power': [14.369810000000001],
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'slew_hl': [0.49631959999999997],
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'slew_lh': [0.49631959999999997],
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'volt_bl': [4.132618],
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'volt_br': [5.573099],
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'write0_power': [13.79953],
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'write1_power': [14.369810000000001]}
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else:
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self.assertTrue(False) # other techs fail
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@ -1,3 +1,4 @@
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#Config file used for collecting data.
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word_size = 1
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num_words = 16
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@ -62,6 +62,8 @@ class openram_test(unittest.TestCase):
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delay_obj.set_load_slew(load, slew)
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delay_obj.set_probe(probe_address="1"*sram.addr_size, probe_data=(sram.word_size-1))
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test_port = delay_obj.read_ports[0] #Only test one port, assumes other ports have similar period.
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delay_obj.create_signal_names()
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delay_obj.create_measurement_names()
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delay_obj.create_measurement_objects()
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delay_obj.find_feasible_period_one_port(test_port)
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return delay_obj.period
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