diff --git a/compiler/tests/21_hspice_delay_test.py b/compiler/tests/21_hspice_delay_test.py
index 8be7152c..a2c40a22 100755
--- a/compiler/tests/21_hspice_delay_test.py
+++ b/compiler/tests/21_hspice_delay_test.py
@@ -51,35 +51,36 @@ class timing_sram_test(openram_test):
         data.update(port_data[0])
      
         if OPTS.tech_name == "freepdk45":
-            golden_data = {'delay_hl': [0.2011],
-                         'delay_lh': [0.2011],
-                         'leakage_power': 0.002,
-                         'min_period': 0.41,
-                         'read0_power': [0.63604],
-                         'read1_power': [0.6120599999999999],
-                         'slew_hl': [0.07078999999999999],
-                         'slew_lh': [0.07078999999999999],
-                         'write0_power': [0.51742],
-                         'write1_power': [0.51095],
-                         'volt_bl': [0.2017],
-                         'volt_br': [1.0765], 
-                         'delay_bl': [0.18114999999999998],
-                         'delay_br': [0.17763]}
+            golden_data = {'delay_bl': [0.19683],
+                         'delay_br': [0.19474],
+                         'delay_hl': [0.20646],
+                         'delay_lh': [0.20646],
+                         'leakage_power': 0.0013155,
+                         'min_period': 0.43,
+                         'read0_power': [0.50758],
+                         'read1_power': [0.48225999999999997],
+                         'slew_hl': [0.045869],
+                         'slew_lh': [0.045869],
+                         'volt_bl': [0.6563],
+                         'volt_br': [1.117],
+                         'write0_power': [0.46124000000000004],
+                         'write1_power': [0.48225999999999997]}
         elif OPTS.tech_name == "scn4m_subm":
-            golden_data = {'delay_hl': [1.3911],
-                         'delay_lh': [1.3911],
-                         'leakage_power': 0.0278488,
-                         'min_period': 2.812,
-                         'read0_power': [22.1183],
-                         'read1_power': [21.4388],
-                         'slew_hl': [0.6],
-                         'slew_lh': [0.6],
-                         'write0_power': [19.4103],
-                         'write1_power': [20.1167],
-                         'volt_bl': [3.1763], 
-                         'volt_br': [5.5731], 
-                         'delay_bl': [1.1133000000000002], 
-                         'delay_br': [0.9958395]}
+            golden_data = {'delay_bl': [1.1029],
+                         'delay_br': [0.9656455999999999],
+                         'delay_hl': [1.288],
+                         'delay_lh': [1.288],
+                         'leakage_power': 0.0273896,
+                         'min_period': 2.578,
+                         'read0_power': [16.9996],
+                         'read1_power': [16.2616],
+                         'slew_hl': [0.47891700000000004],
+                         'slew_lh': [0.47891700000000004],
+                         'volt_bl': [4.2155],
+                         'volt_br': [5.8142],
+                         'write0_power': [16.0656],
+                         'write1_power': [16.2616]}
+
         else:
             self.assertTrue(False) # other techs fail
         # Check if no too many or too few results
diff --git a/compiler/tests/21_ngspice_delay_test.py b/compiler/tests/21_ngspice_delay_test.py
index 98f01e53..5af44e69 100755
--- a/compiler/tests/21_ngspice_delay_test.py
+++ b/compiler/tests/21_ngspice_delay_test.py
@@ -51,35 +51,36 @@ class timing_sram_test(openram_test):
         data.update(port_data[0])
 
         if OPTS.tech_name == "freepdk45":
-            golden_data = {'delay_bl': [0.1840938],
-                           'delay_br': [0.1804373],
-                           'delay_hl': [0.2130831], 
-                           'delay_lh': [0.2130831],
-                           'leakage_power': 0.001595639, 
-                           'min_period': 0.527,
-                           'read0_power': [0.4852456],
-                           'read1_power': [0.46341889999999997],
-                           'slew_hl': [0.07351041999999999],
-                           'slew_lh': [0.07351041999999999],
-                           'volt_bl': [0.1954744],
-                           'volt_br': [1.058266],
-                           'write0_power': [0.4065201],
-                           'write1_power': [0.46341889999999997]}
+            golden_data = {'delay_bl': [0.2003652],
+                         'delay_br': [0.198698],
+                         'delay_hl': [0.2108836],
+                         'delay_lh': [0.2108836],
+                         'leakage_power': 0.001564799,
+                         'min_period': 0.508,
+                         'read0_power': [0.43916689999999997],
+                         'read1_power': [0.4198608],
+                         'slew_hl': [0.0455126],
+                         'slew_lh': [0.0455126],
+                         'volt_bl': [0.6472883],
+                         'volt_br': [1.114024],
+                         'write0_power': [0.40681890000000004],
+                         'write1_power': [0.4198608]}
         elif OPTS.tech_name == "scn4m_subm":
-            golden_data = {'delay_hl': [1.610911],
-                         'delay_lh': [1.610911],
-                         'leakage_power': 0.0023593859999999998,
+            golden_data = {'delay_bl': [1.3937359999999999],
+                         'delay_br': [1.2596429999999998],
+                         'delay_hl': [1.5747600000000002],
+                         'delay_lh': [1.5747600000000002],
+                         'leakage_power': 0.00195795,
                          'min_period': 3.281,
-                         'read0_power': [20.763569999999998],
-                         'read1_power': [20.32745],
-                         'slew_hl': [0.7986348999999999],
-                         'slew_lh': [0.7986348999999999],
-                         'write0_power': [17.58272],
-                         'write1_power': [18.523419999999998],
-                         'volt_bl': [3.1763], 
-                         'volt_br': [5.5731], 
-                         'delay_bl': [1.1133000000000002], 
-                         'delay_br': [0.9958395]}
+                         'read0_power': [14.92874],
+                         'read1_power': [14.369810000000001],
+                         'slew_hl': [0.49631959999999997],
+                         'slew_lh': [0.49631959999999997],
+                         'volt_bl': [4.132618],
+                         'volt_br': [5.573099],
+                         'write0_power': [13.79953],
+                         'write1_power': [14.369810000000001]}
+
         else:
             self.assertTrue(False) # other techs fail
 
diff --git a/compiler/tests/config_data.py b/compiler/tests/config_data.py
index 08168bc3..f81a2451 100755
--- a/compiler/tests/config_data.py
+++ b/compiler/tests/config_data.py
@@ -1,3 +1,4 @@
+#Config file used for collecting data.
 word_size = 1
 num_words = 16
 
diff --git a/compiler/tests/testutils.py b/compiler/tests/testutils.py
index 74d97960..ee7f1412 100755
--- a/compiler/tests/testutils.py
+++ b/compiler/tests/testutils.py
@@ -62,6 +62,8 @@ class openram_test(unittest.TestCase):
         delay_obj.set_load_slew(load, slew)
         delay_obj.set_probe(probe_address="1"*sram.addr_size, probe_data=(sram.word_size-1))
         test_port = delay_obj.read_ports[0] #Only test one port, assumes other ports have similar period.
+        delay_obj.create_signal_names()
+        delay_obj.create_measurement_names()
         delay_obj.create_measurement_objects()
         delay_obj.find_feasible_period_one_port(test_port) 
         return delay_obj.period