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Adjusted test values to account for recent changes.

This commit is contained in:
Hunter Nichols 2019-02-05 00:43:16 -08:00
parent 543e0a1b9a
commit e3d003d410
4 changed files with 60 additions and 55 deletions
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57
compiler/tests/21_hspice_delay_test.py
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@ -51,35 +51,36 @@ class timing_sram_test(openram_test):
data.update(port_data[0]) data.update(port_data[0])
if OPTS.tech_name == "freepdk45": if OPTS.tech_name == "freepdk45":
golden_data = {'delay_hl': [0.2011], golden_data = {'delay_bl': [0.19683],
'delay_lh': [0.2011], 'delay_br': [0.19474],
'leakage_power': 0.002, 'delay_hl': [0.20646],
'min_period': 0.41, 'delay_lh': [0.20646],
'read0_power': [0.63604], 'leakage_power': 0.0013155,
'read1_power': [0.6120599999999999], 'min_period': 0.43,
'slew_hl': [0.07078999999999999], 'read0_power': [0.50758],
'slew_lh': [0.07078999999999999], 'read1_power': [0.48225999999999997],
'write0_power': [0.51742], 'slew_hl': [0.045869],
'write1_power': [0.51095], 'slew_lh': [0.045869],
'volt_bl': [0.2017], 'volt_bl': [0.6563],
'volt_br': [1.0765], 'volt_br': [1.117],
'delay_bl': [0.18114999999999998], 'write0_power': [0.46124000000000004],
'delay_br': [0.17763]} 'write1_power': [0.48225999999999997]}
elif OPTS.tech_name == "scn4m_subm": elif OPTS.tech_name == "scn4m_subm":
golden_data = {'delay_hl': [1.3911], golden_data = {'delay_bl': [1.1029],
'delay_lh': [1.3911], 'delay_br': [0.9656455999999999],
'leakage_power': 0.0278488, 'delay_hl': [1.288],
'min_period': 2.812, 'delay_lh': [1.288],
'read0_power': [22.1183], 'leakage_power': 0.0273896,
'read1_power': [21.4388], 'min_period': 2.578,
'slew_hl': [0.6], 'read0_power': [16.9996],
'slew_lh': [0.6], 'read1_power': [16.2616],
'write0_power': [19.4103], 'slew_hl': [0.47891700000000004],
'write1_power': [20.1167], 'slew_lh': [0.47891700000000004],
'volt_bl': [3.1763], 'volt_bl': [4.2155],
'volt_br': [5.5731], 'volt_br': [5.8142],
'delay_bl': [1.1133000000000002], 'write0_power': [16.0656],
'delay_br': [0.9958395]} 'write1_power': [16.2616]}
else: else:
self.assertTrue(False) # other techs fail self.assertTrue(False) # other techs fail
# Check if no too many or too few results # Check if no too many or too few results

55
compiler/tests/21_ngspice_delay_test.py
View File

@ -51,35 +51,36 @@ class timing_sram_test(openram_test):
data.update(port_data[0]) data.update(port_data[0])
if OPTS.tech_name == "freepdk45": if OPTS.tech_name == "freepdk45":
golden_data = {'delay_bl': [0.1840938], golden_data = {'delay_bl': [0.2003652],
'delay_br': [0.1804373], 'delay_br': [0.198698],
'delay_hl': [0.2130831], 'delay_hl': [0.2108836],
'delay_lh': [0.2130831], 'delay_lh': [0.2108836],
'leakage_power': 0.001595639, 'leakage_power': 0.001564799,
'min_period': 0.527, 'min_period': 0.508,
'read0_power': [0.4852456], 'read0_power': [0.43916689999999997],
'read1_power': [0.46341889999999997], 'read1_power': [0.4198608],
'slew_hl': [0.07351041999999999], 'slew_hl': [0.0455126],
'slew_lh': [0.07351041999999999], 'slew_lh': [0.0455126],
'volt_bl': [0.1954744], 'volt_bl': [0.6472883],
'volt_br': [1.058266], 'volt_br': [1.114024],
'write0_power': [0.4065201], 'write0_power': [0.40681890000000004],
'write1_power': [0.46341889999999997]} 'write1_power': [0.4198608]}
elif OPTS.tech_name == "scn4m_subm": elif OPTS.tech_name == "scn4m_subm":
golden_data = {'delay_hl': [1.610911], golden_data = {'delay_bl': [1.3937359999999999],
'delay_lh': [1.610911], 'delay_br': [1.2596429999999998],
'leakage_power': 0.0023593859999999998, 'delay_hl': [1.5747600000000002],
'delay_lh': [1.5747600000000002],
'leakage_power': 0.00195795,
'min_period': 3.281, 'min_period': 3.281,
'read0_power': [20.763569999999998], 'read0_power': [14.92874],
'read1_power': [20.32745], 'read1_power': [14.369810000000001],
'slew_hl': [0.7986348999999999], 'slew_hl': [0.49631959999999997],
'slew_lh': [0.7986348999999999], 'slew_lh': [0.49631959999999997],
'write0_power': [17.58272], 'volt_bl': [4.132618],
'write1_power': [18.523419999999998], 'volt_br': [5.573099],
'volt_bl': [3.1763], 'write0_power': [13.79953],
'volt_br': [5.5731], 'write1_power': [14.369810000000001]}
'delay_bl': [1.1133000000000002],
'delay_br': [0.9958395]}
else: else:
self.assertTrue(False) # other techs fail self.assertTrue(False) # other techs fail

1
compiler/tests/config_data.py
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@ -1,3 +1,4 @@
#Config file used for collecting data.
word_size = 1 word_size = 1
num_words = 16 num_words = 16

2
compiler/tests/testutils.py
View File

@ -62,6 +62,8 @@ class openram_test(unittest.TestCase):
delay_obj.set_load_slew(load, slew) delay_obj.set_load_slew(load, slew)
delay_obj.set_probe(probe_address="1"*sram.addr_size, probe_data=(sram.word_size-1)) delay_obj.set_probe(probe_address="1"*sram.addr_size, probe_data=(sram.word_size-1))
test_port = delay_obj.read_ports[0] #Only test one port, assumes other ports have similar period. test_port = delay_obj.read_ports[0] #Only test one port, assumes other ports have similar period.
delay_obj.create_signal_names()
delay_obj.create_measurement_names()
delay_obj.create_measurement_objects() delay_obj.create_measurement_objects()
delay_obj.find_feasible_period_one_port(test_port) delay_obj.find_feasible_period_one_port(test_port)
return delay_obj.period return delay_obj.period