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Adjusted test values to account for recent changes.

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Hunter Nichols
2019-02-05 00:43:16 -08:00
parent 543e0a1b9a
commit e3d003d410
4 changed files with 60 additions and 55 deletions
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compiler/tests/testutils.py
+2
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@@ -62,6 +62,8 @@ class openram_test(unittest.TestCase):
delay_obj.set_load_slew(load, slew)
delay_obj.set_probe(probe_address="1"*sram.addr_size, probe_data=(sram.word_size-1))
test_port = delay_obj.read_ports[0] #Only test one port, assumes other ports have similar period.
delay_obj.create_signal_names()
delay_obj.create_measurement_names()
delay_obj.create_measurement_objects()
delay_obj.find_feasible_period_one_port(test_port)
return delay_obj.period