mirror of https://github.com/VLSIDA/OpenRAM.git
Update replica column call to new refactor
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@ -29,6 +29,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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self.column_size = cols
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self.column_size = cols
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self.row_size = rows
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self.row_size = rows
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# This is how many RBLs are in all the arrays
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# This is how many RBLs are in all the arrays
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self.rbl = rbl
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self.left_rbl = rbl[0]
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self.left_rbl = rbl[0]
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self.right_rbl = rbl[1]
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self.right_rbl = rbl[1]
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# This is how many RBLs are added to THIS array
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# This is how many RBLs are added to THIS array
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@ -110,8 +111,7 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
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column_offset = self.left_rbl + 1
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column_offset = self.left_rbl + 1
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self.replica_columns[bit] = factory.create(module_type="replica_column",
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self.replica_columns[bit] = factory.create(module_type="replica_column",
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rows=self.row_size,
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rows=self.row_size,
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left_rbl=self.add_left_rbl,
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rbl=self.rbl,
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right_rbl=self.add_right_rbl,
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column_offset=column_offset,
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column_offset=column_offset,
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replica_bit=replica_bit)
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replica_bit=replica_bit)
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self.add_mod(self.replica_columns[bit])
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self.add_mod(self.replica_columns[bit])
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