Simple version without lvs(rutiime problem with magic

2026-09-04 00:40:09 +02:00 · 2024-07-30 15:04:47 +02:00
parent e6ca825157
commit e3170abd01
4 changed files with 51 additions and 37 deletions
@@ -1273,7 +1273,7 @@ class sram_1bank(design, verilog, lef):
        if len(route_map) > 0:

            # This layer stack must be different than the column addr dff layer stack
-            layer_stack = self.m3_stack
+            layer_stack = self.m2_stack
            if port == 0:
                # This is relative to the bank at 0,0 or the s_en which is routed on M3 also
                if "s_en" in self.control_logic_insts[port].mod.pin_map: