diff --git a/compiler/modules/sram_new.py b/compiler/modules/sram_new.py index aa813084..d16bd7ec 100644 --- a/compiler/modules/sram_new.py +++ b/compiler/modules/sram_new.py @@ -1273,7 +1273,7 @@ class sram_1bank(design, verilog, lef): if len(route_map) > 0: # This layer stack must be different than the column addr dff layer stack - layer_stack = self.m3_stack + layer_stack = self.m2_stack if port == 0: # This is relative to the bank at 0,0 or the s_en which is routed on M3 also if "s_en" in self.control_logic_insts[port].mod.pin_map: diff --git a/compiler/router/signal_escape_router.py b/compiler/router/signal_escape_router.py index 6f79509a..c0b6749a 100644 --- a/compiler/router/signal_escape_router.py +++ b/compiler/router/signal_escape_router.py @@ -24,6 +24,9 @@ class signal_escape_router(router): # New pins are the side supply pins self.new_pins = {} + + # Use for add distance of dout pins at the perimeter + self.distance = 0 def route(self, pin_names): @@ -205,42 +208,23 @@ class signal_escape_router(router): #fake_center = vector(ll.x - self.track_wire * 2, c.y) # test if here we could change the pin position at the layout # relocate the pin position + pattern = r'^dout' + if re.match(pattern, pin.name): + if edge == "bottom":# change to the east + vertical = True + fake_center = vector(ur.x + self.track_wire * 2, ll.y + 30 + self.distance) + self.distance += 1 + else: + if edge == "top":# change to the west + vertical = True + fake_center = vector(ll.x - self.track_wire * 2, ur.y - 30 - self.distance) + self.distance += 1 """ pattern = r'^addr0_1' if re.match(pattern, pin.name): vertical = True fake_center = vector(ll.x - self.track_wire * 2, c.y + self.track_wire * 4)# fix still do not know how to control the distance between every fake pin #do not know why after this, all fake out pins are put at the same position -> because the originl inside pin has same y? - pattern = r'^addr0_2' - if re.match(pattern, pin.name): - vertical = True - fake_center = vector(ll.x - self.track_wire * 2, c.y + self.track_wire * 8)# fix still do not know how to control the distance between every fake pin - #do not know why after this, all fake out pins are put at the same position -> because the originl inside pin has same y? - pattern = r'^addr0_3' - if re.match(pattern, pin.name): - vertical = True - fake_center = vector(ll.x - self.track_wire * 2, c.y + self.track_wire*12)# fix still do not know how to control the distance between every fake pin - #do not know why after this, all fake out pins are put at the same position -> because the originl inside pin has same y? - pattern = r'^addr0_4' - if re.match(pattern, pin.name): - vertical = True - fake_center = vector(ll.x - self.track_wire * 2, c.y + self.track_wire*16)# fix still do not know how to control the distance between every fake pin - #do not know why after this, all fake out pins are put at the same position -> because the originl inside pin has same y? - pattern = r'^p_en_bar0' - if re.match(pattern, pin.name): - vertical = True - fake_center = vector(ll.x - self.track_wire * 2, c.y)# fix still do not know how to control the distance between every fake pin - #do not know why after this, all fake out pins are put at the same position -> because the originl inside pin has same y? - pattern = r'^s_en0' - if re.match(pattern, pin.name): - vertical = True - fake_center = vector(ll.x - self.track_wire * 2, c.y + self.track_width *3)# fix still do not know how to control the distance between every fake pin - #do not know why after this, all fake out pins are put at the same position -> because the originl inside pin has same y? - pattern = r'^w_en0' - if re.match(pattern, pin.name): - vertical = True - fake_center = vector(ll.x - self.track_wire * 2, c.y + self.track_width * 6)# fix still do not know how to control the distance between every fake pin - #do not know why after this, all fake out pins are put at the same position -> because the originl inside pin has same y? """ # Create the fake pin shape layer = self.get_layer(int(not vertical)) diff --git a/compiler/sram_new_test.py b/compiler/sram_new_test.py index 228b3874..01a0b814 100644 --- a/compiler/sram_new_test.py +++ b/compiler/sram_new_test.py @@ -54,10 +54,38 @@ class sram(): self.s = sram(name, sram_config) self.s.create_netlist()# not placed & routed jet - #self.s_tmp = copy.deepcopy(self.s) # need deepcopy if not OPTS.netlist_only: i = 0 supply_route_not_found = False + while i < (OPTS.word_size + 100): + print("current iteration: i = {0}".format(i)) + try: + self.s.create_layout_recrusive(position_add=i) + except AssertionError as e: + supply_route_not_found = True + if i == 99:# failed in rounting + debug.error("Failed in rounting", -1) + break + + + if (supply_route_not_found): + del self.s + self.s = sram(name, sram_config) + self.s.create_netlist() + if i == 0:# after first try + i = OPTS.word_size + 20 + else: + i = i + 1 + supply_route_not_found = False + else:# successfully routed + break + '''#old version + self.s = sram(name, sram_config) + self.s.create_netlist()# not placed & routed jet + #self.s_tmp = copy.deepcopy(self.s) # need deepcopy + if not OPTS.netlist_only: + i = 98 + supply_route_not_found = False #self.s_tmp = copy.deepcopy(self.s) # need deepcopy while i < 100: print("current iteration: {0}".format(i)) @@ -80,7 +108,7 @@ class sram(): else:# successfully routed #self.s = copy.deepcopy(self.s_tmp) # need deepcopy break - + ''' if not OPTS.is_unit_test: print_time("SRAM creation", datetime.datetime.now(), start_time) @@ -134,14 +162,14 @@ class sram(): spname = OPTS.output_path + self.s.name + ".sp" debug.print_raw("SP: Writing to {0}".format(spname)) self.sp_write(spname) - + ''' # Save a functional simulation file with default period functional(self.s, spname, cycles=200, output_path=OPTS.output_path) print_time("Spice writing", datetime.datetime.now(), start_time) - + # Save stimulus and measurement file start_time = datetime.datetime.now() debug.print_raw("DELAY: Writing stimulus...") @@ -156,7 +184,7 @@ class sram(): d.targ_write_ports = [self.s.write_ports[0]] d.write_delay_stimulus() print_time("DELAY", datetime.datetime.now(), start_time) - + ''' # Save trimmed spice file temp_trim_sp = "{0}trimmed.sp".format(OPTS.output_path) self.sp_write(temp_trim_sp, lvs=False, trim=True) diff --git a/macros/sram_configs/sky130_sram_common.py b/macros/sram_configs/sky130_sram_common.py index 445c88cc..415e80f2 100644 --- a/macros/sram_configs/sky130_sram_common.py +++ b/macros/sram_configs/sky130_sram_common.py @@ -10,8 +10,10 @@ nominal_corner_only = True #local_array_size = 16 route_supplies = "ring" +#supply_pin_type = "top" #route_supplies = "left" -check_lvsdrc = True +#route_supplies = False +check_lvsdrc = False uniquify = True #perimeter_pins = False #netlist_only = True