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Add assert to lef and verilog unit test. Fix verilog files in golden results.

This commit is contained in:
Matt Guthaus 2019-01-11 16:42:50 -08:00
parent a7dd62b0e5
commit e210ef2a41
4 changed files with 88 additions and 65 deletions
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5
compiler/tests/24_lef_sram_test.py
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@ -36,10 +36,7 @@ class lef_test(openram_test):
# let's diff the result with a golden model # let's diff the result with a golden model
golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),leffile) golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),leffile)
self.isdiff(lefname,golden) self.assertTrue(self.isdiff(lefname,golden))
os.system("rm {0}".format(gdsname))
os.system("rm {0}".format(lefname))
globals.end_openram() globals.end_openram()

4
compiler/tests/25_verilog_sram_test.py
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@ -33,9 +33,7 @@ class verilog_test(openram_test):
# let's diff the result with a golden model # let's diff the result with a golden model
golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),vfile) golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),vfile)
self.isdiff(vname,golden) self.assertTrue(self.isdiff(vname,golden))
os.system("rm {0}".format(vname))
globals.end_openram() globals.end_openram()

72
compiler/tests/golden/sram_2_16_1_freepdk45.v
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@ -2,46 +2,60 @@
// Words: 16 // Words: 16
// Word size: 2 // Word size: 2
module sram_2_16_1_freepdk45(DATA,ADDR,CSb,WEb,OEb,clk); module sram_2_16_1_freepdk45(
// Port 0: RW
clk0,csb0,web0,ADDR0,DIN0,DOUT0
);
parameter DATA_WIDTH = 2 ; parameter DATA_WIDTH = 2 ;
parameter ADDR_WIDTH = 4 ; parameter ADDR_WIDTH = 4 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH; parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3 ; parameter DELAY = 3 ;
inout [DATA_WIDTH-1:0] DATA; input clk0; // clock
input [ADDR_WIDTH-1:0] ADDR; input csb0; // active low chip select
input CSb; // active low chip select input web0; // active low write control
input WEb; // active low write control input [ADDR_WIDTH-1:0] ADDR0;
input OEb; // active output enable input [DATA_WIDTH-1:0] DIN0;
input clk; // clock output [DATA_WIDTH-1:0] DOUT0;
reg [DATA_WIDTH-1:0] data_out ; reg csb0_reg;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; reg web0_reg;
reg [ADDR_WIDTH-1:0] ADDR0_reg;
reg [DATA_WIDTH-1:0] DIN0_reg;
reg [DATA_WIDTH-1:0] DOUT0;
// Tri-State Buffer control // All inputs are registers
// output : When WEb = 1, oeb = 0, csb = 0 always @(posedge clk0)
assign DATA = (!CSb && !OEb && WEb) ? data_out : 2'bz; begin
csb0_reg = csb0;
// Memory Write Block web0_reg = web0;
// Write Operation : When WEb = 0, CSb = 0 ADDR0_reg = ADDR0;
always @ (posedge clk) DIN0_reg = DIN0;
begin : MEM_WRITE DOUT0 = 2'bx;
if ( !CSb && !WEb ) begin if ( !csb0_reg && web0_reg )
mem[ADDR] = DATA; $display($time," Reading %m ADDR0=%b DOUT0=%b",ADDR0_reg,mem[ADDR0_reg]);
$display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA); if ( !csb0_reg && !web0_reg )
end $display($time," Writing %m ADDR0=%b DIN0=%b",ADDR0_reg,DIN0_reg);
end end
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
// Memory Read Block // Memory Write Block Port 0
// Read Operation : When WEb = 1, CSb = 0 // Write Operation : When web0 = 0, csb0 = 0
always @ (posedge clk) always @ (negedge clk0)
begin : MEM_READ begin : MEM_WRITE0
if (!CSb && WEb) begin if ( !csb0_reg && !web0_reg )
data_out <= #(DELAY) mem[ADDR]; mem[ADDR0_reg] = DIN0_reg;
$display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]); end
end
// Memory Read Block Port 0
// Read Operation : When web0 = 1, csb0 = 0
always @ (negedge clk0)
begin : MEM_READ0
if (!csb0_reg && web0_reg)
DOUT0 <= #(DELAY) mem[ADDR0_reg];
end end
endmodule endmodule

72
compiler/tests/golden/sram_2_16_1_scn4m_subm.v
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@ -2,46 +2,60 @@
// Words: 16 // Words: 16
// Word size: 2 // Word size: 2
module sram_2_16_1_scn4m_subm(DATA,ADDR,CSb,WEb,OEb,clk); module sram_2_16_1_scn4m_subm(
// Port 0: RW
clk0,csb0,web0,ADDR0,DIN0,DOUT0
);
parameter DATA_WIDTH = 2 ; parameter DATA_WIDTH = 2 ;
parameter ADDR_WIDTH = 4 ; parameter ADDR_WIDTH = 4 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH; parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3 ; parameter DELAY = 3 ;
inout [DATA_WIDTH-1:0] DATA; input clk0; // clock
input [ADDR_WIDTH-1:0] ADDR; input csb0; // active low chip select
input CSb; // active low chip select input web0; // active low write control
input WEb; // active low write control input [ADDR_WIDTH-1:0] ADDR0;
input OEb; // active output enable input [DATA_WIDTH-1:0] DIN0;
input clk; // clock output [DATA_WIDTH-1:0] DOUT0;
reg [DATA_WIDTH-1:0] data_out ; reg csb0_reg;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; reg web0_reg;
reg [ADDR_WIDTH-1:0] ADDR0_reg;
reg [DATA_WIDTH-1:0] DIN0_reg;
reg [DATA_WIDTH-1:0] DOUT0;
// Tri-State Buffer control // All inputs are registers
// output : When WEb = 1, oeb = 0, csb = 0 always @(posedge clk0)
assign DATA = (!CSb && !OEb && WEb) ? data_out : 2'bz; begin
csb0_reg = csb0;
// Memory Write Block web0_reg = web0;
// Write Operation : When WEb = 0, CSb = 0 ADDR0_reg = ADDR0;
always @ (posedge clk) DIN0_reg = DIN0;
begin : MEM_WRITE DOUT0 = 2'bx;
if ( !CSb && !WEb ) begin if ( !csb0_reg && web0_reg )
mem[ADDR] = DATA; $display($time," Reading %m ADDR0=%b DOUT0=%b",ADDR0_reg,mem[ADDR0_reg]);
$display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA); if ( !csb0_reg && !web0_reg )
end $display($time," Writing %m ADDR0=%b DIN0=%b",ADDR0_reg,DIN0_reg);
end end
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
// Memory Read Block // Memory Write Block Port 0
// Read Operation : When WEb = 1, CSb = 0 // Write Operation : When web0 = 0, csb0 = 0
always @ (posedge clk) always @ (negedge clk0)
begin : MEM_READ begin : MEM_WRITE0
if (!CSb && WEb) begin if ( !csb0_reg && !web0_reg )
data_out <= #(DELAY) mem[ADDR]; mem[ADDR0_reg] = DIN0_reg;
$display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]); end
end
// Memory Read Block Port 0
// Read Operation : When web0 = 1, csb0 = 0
always @ (negedge clk0)
begin : MEM_READ0
if (!csb0_reg && web0_reg)
DOUT0 <= #(DELAY) mem[ADDR0_reg];
end end
endmodule endmodule