From e210ef2a4109fd6e8e946ab3d38db9624376aaa8 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Fri, 11 Jan 2019 16:42:50 -0800 Subject: [PATCH] Add assert to lef and verilog unit test. Fix verilog files in golden results. --- compiler/tests/24_lef_sram_test.py | 5 +- compiler/tests/25_verilog_sram_test.py | 4 +- compiler/tests/golden/sram_2_16_1_freepdk45.v | 72 +++++++++++-------- .../tests/golden/sram_2_16_1_scn4m_subm.v | 72 +++++++++++-------- 4 files changed, 88 insertions(+), 65 deletions(-) diff --git a/compiler/tests/24_lef_sram_test.py b/compiler/tests/24_lef_sram_test.py index 2d90d12b..983038a2 100755 --- a/compiler/tests/24_lef_sram_test.py +++ b/compiler/tests/24_lef_sram_test.py @@ -36,10 +36,7 @@ class lef_test(openram_test): # let's diff the result with a golden model golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),leffile) - self.isdiff(lefname,golden) - - os.system("rm {0}".format(gdsname)) - os.system("rm {0}".format(lefname)) + self.assertTrue(self.isdiff(lefname,golden)) globals.end_openram() diff --git a/compiler/tests/25_verilog_sram_test.py b/compiler/tests/25_verilog_sram_test.py index 4aa2fce7..f98475b4 100755 --- a/compiler/tests/25_verilog_sram_test.py +++ b/compiler/tests/25_verilog_sram_test.py @@ -33,9 +33,7 @@ class verilog_test(openram_test): # let's diff the result with a golden model golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),vfile) - self.isdiff(vname,golden) - - os.system("rm {0}".format(vname)) + self.assertTrue(self.isdiff(vname,golden)) globals.end_openram() diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45.v b/compiler/tests/golden/sram_2_16_1_freepdk45.v index 94bd09e2..025350bc 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45.v +++ b/compiler/tests/golden/sram_2_16_1_freepdk45.v @@ -2,46 +2,60 @@ // Words: 16 // Word size: 2 -module sram_2_16_1_freepdk45(DATA,ADDR,CSb,WEb,OEb,clk); +module sram_2_16_1_freepdk45( +// Port 0: RW + clk0,csb0,web0,ADDR0,DIN0,DOUT0 + ); parameter DATA_WIDTH = 2 ; parameter ADDR_WIDTH = 4 ; parameter RAM_DEPTH = 1 << ADDR_WIDTH; + // FIXME: This delay is arbitrary. parameter DELAY = 3 ; - inout [DATA_WIDTH-1:0] DATA; - input [ADDR_WIDTH-1:0] ADDR; - input CSb; // active low chip select - input WEb; // active low write control - input OEb; // active output enable - input clk; // clock + input clk0; // clock + input csb0; // active low chip select + input web0; // active low write control + input [ADDR_WIDTH-1:0] ADDR0; + input [DATA_WIDTH-1:0] DIN0; + output [DATA_WIDTH-1:0] DOUT0; - reg [DATA_WIDTH-1:0] data_out ; - reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; + reg csb0_reg; + reg web0_reg; + reg [ADDR_WIDTH-1:0] ADDR0_reg; + reg [DATA_WIDTH-1:0] DIN0_reg; + reg [DATA_WIDTH-1:0] DOUT0; - // Tri-State Buffer control - // output : When WEb = 1, oeb = 0, csb = 0 - assign DATA = (!CSb && !OEb && WEb) ? data_out : 2'bz; - - // Memory Write Block - // Write Operation : When WEb = 0, CSb = 0 - always @ (posedge clk) - begin : MEM_WRITE - if ( !CSb && !WEb ) begin - mem[ADDR] = DATA; - $display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA); - end + // All inputs are registers + always @(posedge clk0) + begin + csb0_reg = csb0; + web0_reg = web0; + ADDR0_reg = ADDR0; + DIN0_reg = DIN0; + DOUT0 = 2'bx; + if ( !csb0_reg && web0_reg ) + $display($time," Reading %m ADDR0=%b DOUT0=%b",ADDR0_reg,mem[ADDR0_reg]); + if ( !csb0_reg && !web0_reg ) + $display($time," Writing %m ADDR0=%b DIN0=%b",ADDR0_reg,DIN0_reg); end +reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; - // Memory Read Block - // Read Operation : When WEb = 1, CSb = 0 - always @ (posedge clk) - begin : MEM_READ - if (!CSb && WEb) begin - data_out <= #(DELAY) mem[ADDR]; - $display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]); - end + // Memory Write Block Port 0 + // Write Operation : When web0 = 0, csb0 = 0 + always @ (negedge clk0) + begin : MEM_WRITE0 + if ( !csb0_reg && !web0_reg ) + mem[ADDR0_reg] = DIN0_reg; + end + + // Memory Read Block Port 0 + // Read Operation : When web0 = 1, csb0 = 0 + always @ (negedge clk0) + begin : MEM_READ0 + if (!csb0_reg && web0_reg) + DOUT0 <= #(DELAY) mem[ADDR0_reg]; end endmodule diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm.v b/compiler/tests/golden/sram_2_16_1_scn4m_subm.v index de4c077c..7017b8a7 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm.v +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm.v @@ -2,46 +2,60 @@ // Words: 16 // Word size: 2 -module sram_2_16_1_scn4m_subm(DATA,ADDR,CSb,WEb,OEb,clk); +module sram_2_16_1_scn4m_subm( +// Port 0: RW + clk0,csb0,web0,ADDR0,DIN0,DOUT0 + ); parameter DATA_WIDTH = 2 ; parameter ADDR_WIDTH = 4 ; parameter RAM_DEPTH = 1 << ADDR_WIDTH; + // FIXME: This delay is arbitrary. parameter DELAY = 3 ; - inout [DATA_WIDTH-1:0] DATA; - input [ADDR_WIDTH-1:0] ADDR; - input CSb; // active low chip select - input WEb; // active low write control - input OEb; // active output enable - input clk; // clock + input clk0; // clock + input csb0; // active low chip select + input web0; // active low write control + input [ADDR_WIDTH-1:0] ADDR0; + input [DATA_WIDTH-1:0] DIN0; + output [DATA_WIDTH-1:0] DOUT0; - reg [DATA_WIDTH-1:0] data_out ; - reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; + reg csb0_reg; + reg web0_reg; + reg [ADDR_WIDTH-1:0] ADDR0_reg; + reg [DATA_WIDTH-1:0] DIN0_reg; + reg [DATA_WIDTH-1:0] DOUT0; - // Tri-State Buffer control - // output : When WEb = 1, oeb = 0, csb = 0 - assign DATA = (!CSb && !OEb && WEb) ? data_out : 2'bz; - - // Memory Write Block - // Write Operation : When WEb = 0, CSb = 0 - always @ (posedge clk) - begin : MEM_WRITE - if ( !CSb && !WEb ) begin - mem[ADDR] = DATA; - $display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA); - end + // All inputs are registers + always @(posedge clk0) + begin + csb0_reg = csb0; + web0_reg = web0; + ADDR0_reg = ADDR0; + DIN0_reg = DIN0; + DOUT0 = 2'bx; + if ( !csb0_reg && web0_reg ) + $display($time," Reading %m ADDR0=%b DOUT0=%b",ADDR0_reg,mem[ADDR0_reg]); + if ( !csb0_reg && !web0_reg ) + $display($time," Writing %m ADDR0=%b DIN0=%b",ADDR0_reg,DIN0_reg); end +reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1]; - // Memory Read Block - // Read Operation : When WEb = 1, CSb = 0 - always @ (posedge clk) - begin : MEM_READ - if (!CSb && WEb) begin - data_out <= #(DELAY) mem[ADDR]; - $display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]); - end + // Memory Write Block Port 0 + // Write Operation : When web0 = 0, csb0 = 0 + always @ (negedge clk0) + begin : MEM_WRITE0 + if ( !csb0_reg && !web0_reg ) + mem[ADDR0_reg] = DIN0_reg; + end + + // Memory Read Block Port 0 + // Read Operation : When web0 = 1, csb0 = 0 + always @ (negedge clk0) + begin : MEM_READ0 + if (!csb0_reg && web0_reg) + DOUT0 <= #(DELAY) mem[ADDR0_reg]; end endmodule