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OpenRAM
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Merge branch 'dev' into s8_single_port

This commit is contained in:
jcirimel 2020-11-03 15:21:03 -08:00
parent d69ca2b1ed a128e0501e
commit e1d7d9dff7
310 changed files with 3204 additions and 3466 deletions
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2
compiler/base/contact.py
View File

@ -34,7 +34,7 @@ class contact(hierarchy_design.hierarchy_design):
# This will ignore the name parameter since # This will ignore the name parameter since
# we can guarantee a unique name here # we can guarantee a unique name here
super().__init__(name) super().__init__(name, name)
debug.info(4, "create contact object {0}".format(name)) debug.info(4, "create contact object {0}".format(name))
self.add_comment("layers: {0}".format(layer_stack)) self.add_comment("layers: {0}".format(layer_stack))

14
compiler/base/design.py
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@ -9,19 +9,27 @@ from hierarchy_design import hierarchy_design
from utils import round_to_grid from utils import round_to_grid
import contact import contact
from tech import preferred_directions from tech import preferred_directions
from tech import cell_properties as props
from globals import OPTS from globals import OPTS
import re import re
import debug
class design(hierarchy_design): class design(hierarchy_design):
""" """
This is the same as the hierarchy_design class except it contains This is the same as the hierarchy_design class except it contains
some DRC/layer constants and analytical models for other modules to reuse. some DRC/layer constants and analytical models for other modules to reuse.
""" """
def __init__(self, name): def __init__(self, name, cell_name=None):
super().__init__(name) # This allows us to use different GDS/spice circuits for hard cells instead of the default ones
# Except bitcell names are generated automatically by the globals.py setup_bitcells routines
# depending on the number of ports.
if name in props.names:
cell_name = props.names[name]
elif not cell_name:
cell_name = name
super().__init__(name, cell_name)
self.setup_multiport_constants() self.setup_multiport_constants()

6
compiler/base/geometry.py
View File

@ -227,7 +227,7 @@ class instance(geometry):
self.mod.gds_write_file(self.gds) self.mod.gds_write_file(self.gds)
# now write an instance of my module/structure # now write an instance of my module/structure
new_layout.addInstance(self.gds, new_layout.addInstance(self.gds,
self.mod.name, self.mod.cell_name,
offsetInMicrons=self.offset, offsetInMicrons=self.offset,
mirror=self.mirror, mirror=self.mirror,
rotate=self.rotate) rotate=self.rotate)
@ -402,11 +402,11 @@ class instance(geometry):
def __str__(self): def __str__(self):
""" override print function output """ """ override print function output """
return "( inst: " + self.name + " @" + str(self.offset) + " mod=" + self.mod.name + " " + self.mirror + " R=" + str(self.rotate) + ")" return "( inst: " + self.name + " @" + str(self.offset) + " mod=" + self.mod.cell_name + " " + self.mirror + " R=" + str(self.rotate) + ")"
def __repr__(self): def __repr__(self):
""" override print function output """ """ override print function output """
return "( inst: " + self.name + " @" + str(self.offset) + " mod=" + self.mod.name + " " + self.mirror + " R=" + str(self.rotate) + ")" return "( inst: " + self.name + " @" + str(self.offset) + " mod=" + self.mod.cell_name + " " + self.mirror + " R=" + str(self.rotate) + ")"
class path(geometry): class path(geometry):

33
compiler/base/hierarchy_design.py
View File

@ -20,9 +20,9 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
""" """
name_map = [] name_map = []
def __init__(self, name): def __init__(self, name, cell_name):
self.gds_file = OPTS.openram_tech + "gds_lib/" + name + ".gds" self.gds_file = OPTS.openram_tech + "gds_lib/" + cell_name + ".gds"
self.sp_file = OPTS.openram_tech + "sp_lib/" + name + ".sp" self.sp_file = OPTS.openram_tech + "sp_lib/" + cell_name + ".sp"
# If we have a separate lvs directory, then all the lvs files # If we have a separate lvs directory, then all the lvs files
# should be in there (all or nothing!) # should be in there (all or nothing!)
@ -33,7 +33,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
lvs_dir = OPTS.openram_tech + lvs_subdir + "/" lvs_dir = OPTS.openram_tech + lvs_subdir + "/"
if os.path.exists(lvs_dir): if os.path.exists(lvs_dir):
self.lvs_file = lvs_dir + name + ".sp" self.lvs_file = lvs_dir + cell_name + ".sp"
else: else:
self.lvs_file = self.sp_file self.lvs_file = self.sp_file
@ -41,8 +41,9 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
self.lvs_errors = "skipped" self.lvs_errors = "skipped"
self.name = name self.name = name
hierarchy_spice.spice.__init__(self, name) self.cell_name = cell_name
hierarchy_layout.layout.__init__(self, name) hierarchy_spice.spice.__init__(self, name, cell_name)
hierarchy_layout.layout.__init__(self, name, cell_name)
self.init_graph_params() self.init_graph_params()
def get_layout_pins(self, inst): def get_layout_pins(self, inst):
@ -76,17 +77,17 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
self.lvs_write(tempspice) self.lvs_write(tempspice)
self.gds_write(tempgds) self.gds_write(tempgds)
# Final verification option does not allow nets to be connected by label. # Final verification option does not allow nets to be connected by label.
self.drc_errors = verify.run_drc(self.name, tempgds, extract=True, final_verification=final_verification) self.drc_errors = verify.run_drc(self.cell_name, tempgds, extract=True, final_verification=final_verification)
self.lvs_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification) self.lvs_errors = verify.run_lvs(self.cell_name, tempgds, tempspice, final_verification=final_verification)
# force_check is used to determine decoder height and other things, so we shouldn't fail # force_check is used to determine decoder height and other things, so we shouldn't fail
# if that flag is set # if that flag is set
if OPTS.inline_lvsdrc and not force_check: if OPTS.inline_lvsdrc and not force_check:
debug.check(self.drc_errors == 0, debug.check(self.drc_errors == 0,
"DRC failed for {0} with {1} error(s)".format(self.name, "DRC failed for {0} with {1} error(s)".format(self.cell_name,
self.drc_errors)) self.drc_errors))
debug.check(self.lvs_errors == 0, debug.check(self.lvs_errors == 0,
"LVS failed for {0} with {1} errors(s)".format(self.name, "LVS failed for {0} with {1} errors(s)".format(self.cell_name,
self.lvs_errors)) self.lvs_errors))
if OPTS.purge_temp: if OPTS.purge_temp:
@ -104,11 +105,11 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
if OPTS.netlist_only: if OPTS.netlist_only:
return return
elif (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): elif (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)):
tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.cell_name)
self.gds_write(tempgds) self.gds_write(tempgds)
num_errors = verify.run_drc(self.name, tempgds, final_verification=final_verification) num_errors = verify.run_drc(self.cell_name, tempgds, final_verification=final_verification)
debug.check(num_errors == 0, debug.check(num_errors == 0,
"DRC failed for {0} with {1} error(s)".format(self.name, "DRC failed for {0} with {1} error(s)".format(self.cell_name,
num_errors)) num_errors))
if OPTS.purge_temp: if OPTS.purge_temp:
@ -125,13 +126,13 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
if OPTS.netlist_only: if OPTS.netlist_only:
return return
elif (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)): elif (not OPTS.is_unit_test and OPTS.check_lvsdrc and (OPTS.inline_lvsdrc or final_verification)):
tempspice = "{0}/{1}.sp".format(OPTS.openram_temp, self.name) tempspice = "{0}/{1}.sp".format(OPTS.openram_temp, self.cell_name)
tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name) tempgds = "{0}/{1}.gds".format(OPTS.openram_temp, self.name)
self.lvs_write(tempspice) self.lvs_write(tempspice)
self.gds_write(tempgds) self.gds_write(tempgds)
num_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification) num_errors = verify.run_lvs(self.name, tempgds, tempspice, final_verification=final_verification)
debug.check(num_errors == 0, debug.check(num_errors == 0,
"LVS failed for {0} with {1} error(s)".format(self.name, "LVS failed for {0} with {1} error(s)".format(self.cell_name,
num_errors)) num_errors))
if OPTS.purge_temp: if OPTS.purge_temp:
os.remove(tempspice) os.remove(tempspice)
@ -217,7 +218,7 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
pins = ",".join(self.pins) pins = ",".join(self.pins)
insts = [" {}".format(x) for x in self.insts] insts = [" {}".format(x) for x in self.insts]
objs = [" {}".format(x) for x in self.objs] objs = [" {}".format(x) for x in self.objs]
s = "********** design {0} **********".format(self.name) s = "********** design {0} **********".format(self.cell_name)
s += "\n pins ({0})={1}\n".format(len(self.pins), pins) s += "\n pins ({0})={1}\n".format(len(self.pins), pins)
s += "\n objs ({0})=\n{1}\n".format(len(self.objs), "\n".join(objs)) s += "\n objs ({0})=\n{1}\n".format(len(self.objs), "\n".join(objs))
s += "\n insts ({0})=\n{1}\n".format(len(self.insts), "\n".join(insts)) s += "\n insts ({0})=\n{1}\n".format(len(self.insts), "\n".join(insts))

8
compiler/base/hierarchy_layout.py
View File

@ -13,6 +13,7 @@ from tech import drc, GDS
from tech import layer as techlayer from tech import layer as techlayer
from tech import layer_indices from tech import layer_indices
from tech import layer_stacks from tech import layer_stacks
from tech import preferred_directions
import os import os
from globals import OPTS from globals import OPTS
from vector import vector from vector import vector
@ -30,8 +31,9 @@ class layout():
layout/netlist and perform LVS/DRC. layout/netlist and perform LVS/DRC.
""" """
def __init__(self, name): def __init__(self, name, cell_name):
self.name = name self.name = name
self.cell_name = cell_name
self.width = None self.width = None
self.height = None self.height = None
self.bounding_box = None self.bounding_box = None
@ -214,7 +216,7 @@ class layout():
# Contacts are not really instances, so skip them # Contacts are not really instances, so skip them
if "contact" not in mod.name: if "contact" not in mod.name:
# Check that the instance name is unique # Check that the instance name is unique
debug.check(name not in self.inst_names, "Duplicate named instance in {0}: {1}".format(self.name, name)) debug.check(name not in self.inst_names, "Duplicate named instance in {0}: {1}".format(self.cell_name, name))
self.inst_names.add(name) self.inst_names.add(name)
self.insts.append(geometry.instance(name, mod, offset, mirror, rotate)) self.insts.append(geometry.instance(name, mod, offset, mirror, rotate))
@ -315,7 +317,7 @@ class layout():
return any_pin return any_pin
except Exception: except Exception:
self.gds_write("missing_pin.gds") self.gds_write("missing_pin.gds")
debug.error("No pin found with name {0} on {1}. Saved as missing_pin.gds.".format(text, self.name), -1) debug.error("No pin found with name {0} on {1}. Saved as missing_pin.gds.".format(text, self.cell_name), -1)
def get_pins(self, text): def get_pins(self, text):
""" """

22
compiler/base/hierarchy_spice.py
View File

@ -10,6 +10,7 @@ import re
import os import os
import math import math
import tech import tech
from pprint import pformat
from delay_data import delay_data from delay_data import delay_data
from wire_spice_model import wire_spice_model from wire_spice_model import wire_spice_model
from power_data import power_data from power_data import power_data
@ -26,8 +27,9 @@ class spice():
Class consisting of a set of modules and instances of these modules Class consisting of a set of modules and instances of these modules
""" """
def __init__(self, name): def __init__(self, name, cell_name):
self.name = name self.name = name
self.cell_name = cell_name
self.valid_signal_types = ["INOUT", "INPUT", "OUTPUT", "POWER", "GROUND"] self.valid_signal_types = ["INOUT", "INPUT", "OUTPUT", "POWER", "GROUND"]
# Holds subckts/mods for this module # Holds subckts/mods for this module
@ -164,7 +166,6 @@ class spice():
num_pins = len(self.insts[-1].mod.pins) num_pins = len(self.insts[-1].mod.pins)
num_args = len(args) num_args = len(args)
if (check and num_pins != num_args): if (check and num_pins != num_args):
from pprint import pformat
if num_pins < num_args: if num_pins < num_args:
mod_pins = self.insts[-1].mod.pins + [""] * (num_args - num_pins) mod_pins = self.insts[-1].mod.pins + [""] * (num_args - num_pins)
arg_pins = args arg_pins = args
@ -181,7 +182,6 @@ class spice():
self.conns.append(args) self.conns.append(args)
if check and (len(self.insts)!=len(self.conns)): if check and (len(self.insts)!=len(self.conns)):
from pprint import pformat
insts_string=pformat(self.insts) insts_string=pformat(self.insts)
conns_string=pformat(self.conns) conns_string=pformat(self.conns)
@ -214,7 +214,7 @@ class spice():
f.close() f.close()
# find the correct subckt line in the file # find the correct subckt line in the file
subckt = re.compile("^.subckt {}".format(self.name), re.IGNORECASE) subckt = re.compile("^.subckt {}".format(self.cell_name), re.IGNORECASE)
subckt_line = list(filter(subckt.search, self.spice))[0] subckt_line = list(filter(subckt.search, self.spice))[0]
# parses line into ports and remove subckt # parses line into ports and remove subckt
self.pins = subckt_line.split(" ")[2:] self.pins = subckt_line.split(" ")[2:]
@ -234,7 +234,7 @@ class spice():
# pins and subckt should be the same # pins and subckt should be the same
# find the correct subckt line in the file # find the correct subckt line in the file
subckt = re.compile("^.subckt {}".format(self.name), re.IGNORECASE) subckt = re.compile("^.subckt {}".format(self.cell_name), re.IGNORECASE)
subckt_line = list(filter(subckt.search, self.lvs))[0] subckt_line = list(filter(subckt.search, self.lvs))[0]
# parses line into ports and remove subckt # parses line into ports and remove subckt
lvs_pins = subckt_line.split(" ")[2:] lvs_pins = subckt_line.split(" ")[2:]
@ -293,7 +293,7 @@ class spice():
return return
# write out the first spice line (the subcircuit) # write out the first spice line (the subcircuit)
sp.write("\n.SUBCKT {0} {1}\n".format(self.name, sp.write("\n.SUBCKT {0} {1}\n".format(self.cell_name,
" ".join(self.pins))) " ".join(self.pins)))
for pin in self.pins: for pin in self.pins:
@ -304,7 +304,7 @@ class spice():
# every instance must have a set of connections, even if it is empty. # every instance must have a set of connections, even if it is empty.
if len(self.insts) != len(self.conns): if len(self.insts) != len(self.conns):
debug.error("{0} : Not all instance pins ({1}) are connected ({2}).".format(self.name, debug.error("{0} : Not all instance pins ({1}) are connected ({2}).".format(self.cell_name,
len(self.insts), len(self.insts),
len(self.conns))) len(self.conns)))
debug.error("Instances: \n" + str(self.insts)) debug.error("Instances: \n" + str(self.insts))
@ -330,9 +330,9 @@ class spice():
else: else:
sp.write("X{0} {1} {2}\n".format(self.insts[i].name, sp.write("X{0} {1} {2}\n".format(self.insts[i].name,
" ".join(self.conns[i]), " ".join(self.conns[i]),
self.insts[i].mod.name)) self.insts[i].mod.cell_name))
sp.write(".ENDS {0}\n".format(self.name)) sp.write(".ENDS {0}\n".format(self.cell_name))
else: else:
# If spice is a hard module, output the spice file contents. # If spice is a hard module, output the spice file contents.
@ -390,7 +390,7 @@ class spice():
.format(self.__class__.__name__)) .format(self.__class__.__name__))
debug.warning("Class {0} name {1}" debug.warning("Class {0} name {1}"
.format(self.__class__.__name__, .format(self.__class__.__name__,
self.name)) self.cell_name))
return None return None
def get_cin(self): def get_cin(self):
@ -408,7 +408,7 @@ class spice():
.format(self.__class__.__name__)) .format(self.__class__.__name__))
debug.warning("Class {0} name {1}" debug.warning("Class {0} name {1}"
.format(self.__class__.__name__, .format(self.__class__.__name__,
self.name)) self.cell_name))
return 0 return 0
def cal_delay_with_rc(self, corner, r, c, slew, swing=0.5): def cal_delay_with_rc(self, corner, r, c, slew, swing=0.5):

99
compiler/base/utils.py
View File

@ -4,10 +4,12 @@
# of Regents for the Oklahoma Agricultural and Mechanical College # of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University) # (acting for and on behalf of Oklahoma State University)
# All rights reserved. # All rights reserved.
#
import os
import math
import gdsMill import gdsMill
import tech import tech
import math
import globals import globals
import debug import debug
from vector import vector from vector import vector
@ -57,10 +59,11 @@ def auto_measure_libcell(pin_list, name, units, lpp):
Return these as a set of properties including the cell width/height too. Return these as a set of properties including the cell width/height too.
""" """
cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds" cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds"
cell_vlsi = gdsMill.VlsiLayout(units=units)
reader = gdsMill.Gds2reader(cell_vlsi)
reader.loadFromFile(cell_gds)
cell_vlsi = _get_gds_reader(units, cell_gds)
# FIXME: This duplicates a lot of functionality of get_gds_size and
# get_gds_pins, it should probably just call those functions?
cell = {} cell = {}
measure_result = cell_vlsi.getLayoutBorder(lpp[0]) measure_result = cell_vlsi.getLayoutBorder(lpp[0])
if measure_result: if measure_result:
@ -73,22 +76,47 @@ def auto_measure_libcell(pin_list, name, units, lpp):
return cell return cell
_GDS_READER_CACHE = {}
def _get_gds_reader(units, gds_filename):
gds_absname = os.path.realpath(gds_filename)
k = (units, gds_absname)
try:
return _GDS_READER_CACHE[k]
except KeyError:
debug.info(4, "Creating VLSI layout from {}".format(gds_absname))
cell_vlsi = gdsMill.VlsiLayout(units=units)
reader = gdsMill.Gds2reader(cell_vlsi)
reader.loadFromFile(gds_absname)
_GDS_READER_CACHE[k] = cell_vlsi
return cell_vlsi
_GDS_SIZE_CACHE = {}
def get_gds_size(name, gds_filename, units, lpp): def get_gds_size(name, gds_filename, units, lpp):
""" """
Open a GDS file and return the size from either the Open a GDS file and return the size from either the
bounding box or a border layer. bounding box or a border layer.
""" """
debug.info(4, "Creating VLSI layout for {}".format(name)) k = (name, os.path.realpath(gds_filename), units, lpp)
cell_vlsi = gdsMill.VlsiLayout(units=units) try:
reader = gdsMill.Gds2reader(cell_vlsi) return _GDS_SIZE_CACHE[k]
reader.loadFromFile(gds_filename) except KeyError:
cell_vlsi = _get_gds_reader(units, gds_filename)
measure_result = cell_vlsi.getLayoutBorder(lpp) measure_result = cell_vlsi.getLayoutBorder(lpp)
if not measure_result: if not measure_result:
debug.info(2, "Layout border failed. Trying to measure size for {}".format(name)) debug.info(2, "Layout border failed. Trying to measure size for {}".format(name))
measure_result = cell_vlsi.measureSize(name) measure_result = cell_vlsi.measureSize(name)
# returns width,height
return measure_result _GDS_SIZE_CACHE[k] = measure_result
# returns width,height
return measure_result
def get_libcell_size(name, units, lpp): def get_libcell_size(name, units, lpp):
@ -101,27 +129,34 @@ def get_libcell_size(name, units, lpp):
return(get_gds_size(name, cell_gds, units, lpp)) return(get_gds_size(name, cell_gds, units, lpp))
_GDS_PINS_CACHE = {}
def get_gds_pins(pin_names, name, gds_filename, units): def get_gds_pins(pin_names, name, gds_filename, units):
""" """
Open a GDS file and find the pins in pin_names as text on a given layer. Open a GDS file and find the pins in pin_names as text on a given layer.
Return these as a rectangle layer pair for each pin. Return these as a rectangle layer pair for each pin.
""" """
cell_vlsi = gdsMill.VlsiLayout(units=units) k = (tuple(pin_names), name, os.path.realpath(gds_filename), units)
reader = gdsMill.Gds2reader(cell_vlsi) try:
reader.loadFromFile(gds_filename) return dict(_GDS_PINS_CACHE[k])
except KeyError:
cell_vlsi = _get_gds_reader(units, gds_filename)
cell = {} cell = {}
for pin_name in pin_names: for pin_name in pin_names:
cell[str(pin_name)] = [] cell[str(pin_name)] = []
pin_list = cell_vlsi.getPinShape(str(pin_name)) pin_list = cell_vlsi.getPinShape(str(pin_name))
for pin_shape in pin_list: for pin_shape in pin_list:
(lpp, boundary) = pin_shape (lpp, boundary) = pin_shape
rect = [vector(boundary[0], boundary[1]), rect = [vector(boundary[0], boundary[1]),
vector(boundary[2], boundary[3])] vector(boundary[2], boundary[3])]
# this is a list because other cells/designs # this is a list because other cells/designs
# may have must-connect pins # may have must-connect pins
cell[str(pin_name)].append(pin_layout(pin_name, rect, lpp)) cell[str(pin_name)].append(pin_layout(pin_name, rect, lpp))
return cell
_GDS_PINS_CACHE[k] = cell
return dict(cell)
def get_libcell_pins(pin_list, name, units): def get_libcell_pins(pin_list, name, units):
@ -132,7 +167,3 @@ def get_libcell_pins(pin_list, name, units):
cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds" cell_gds = OPTS.openram_tech + "gds_lib/" + str(name) + ".gds"
return(get_gds_pins(pin_list, name, cell_gds, units)) return(get_gds_pins(pin_list, name, cell_gds, units))

21
compiler/bitcells/bitcell.py
View File

@ -6,9 +6,8 @@
# All rights reserved. # All rights reserved.
# #
import debug import debug
import utils
from tech import GDS, layer
from tech import cell_properties as props from tech import cell_properties as props
from globals import OPTS
import bitcell_base import bitcell_base
@ -20,8 +19,6 @@ class bitcell(bitcell_base.bitcell_base):
library. library.
""" """
# If we have a split WL bitcell, if not be backwards
# compatible in the tech file
pin_names = [props.bitcell.cell_6t.pin.bl, pin_names = [props.bitcell.cell_6t.pin.bl,
props.bitcell.cell_6t.pin.br, props.bitcell.cell_6t.pin.br,
props.bitcell.cell_6t.pin.wl, props.bitcell.cell_6t.pin.wl,
@ -30,20 +27,12 @@ class bitcell(bitcell_base.bitcell_base):
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
storage_nets = ['Q', 'Q_bar'] storage_nets = ['Q', 'Q_bar']
(width, height) = utils.get_libcell_size("cell_6t", def __init__(self, name, cell_name=None):
GDS["unit"], if not cell_name:
layer["boundary"]) cell_name = OPTS.bitcell_name
pin_map = utils.get_libcell_pins(pin_names, "cell_6t", GDS["unit"]) super().__init__(name, cell_name)
def __init__(self, name=""):
# Ignore the name argument
bitcell_base.bitcell_base.__init__(self, "cell_6t")
debug.info(2, "Create bitcell") debug.info(2, "Create bitcell")
self.width = bitcell.width
self.height = bitcell.height
self.pin_map = bitcell.pin_map
self.add_pin_types(self.type_list)
self.nets_match = self.do_nets_exist(self.storage_nets) self.nets_match = self.do_nets_exist(self.storage_nets)
def get_all_wl_names(self): def get_all_wl_names(self):

22
compiler/bitcells/bitcell_1rw_1r.py
View File

@ -6,11 +6,9 @@
# All rights reserved. # All rights reserved.
# #
import debug import debug
import utils
from tech import GDS, layer, parameter, drc
from tech import cell_properties as props from tech import cell_properties as props
import logical_effort
import bitcell_base import bitcell_base
from globals import OPTS
class bitcell_1rw_1r(bitcell_base.bitcell_base): class bitcell_1rw_1r(bitcell_base.bitcell_base):
@ -29,27 +27,19 @@ class bitcell_1rw_1r(bitcell_base.bitcell_base):
props.bitcell.cell_1rw1r.pin.wl1, props.bitcell.cell_1rw1r.pin.wl1,
props.bitcell.cell_1rw1r.pin.vdd, props.bitcell.cell_1rw1r.pin.vdd,
props.bitcell.cell_1rw1r.pin.gnd] props.bitcell.cell_1rw1r.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT",
"INPUT", "INPUT", "POWER", "GROUND"] "INPUT", "INPUT", "POWER", "GROUND"]
storage_nets = ['Q', 'Q_bar'] storage_nets = ['Q', 'Q_bar']
(width, height) = utils.get_libcell_size("cell_1rw_1r",
GDS["unit"],
layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "cell_1rw_1r", GDS["unit"])
def __init__(self, name=""): def __init__(self, name, cell_name=None):
# Ignore the name argument if not cell_name:
bitcell_base.bitcell_base.__init__(self, "cell_1rw_1r") cell_name = OPTS.bitcell_name
super().__init__(name, cell_name)
debug.info(2, "Create bitcell with 1RW and 1R Port") debug.info(2, "Create bitcell with 1RW and 1R Port")
self.width = bitcell_1rw_1r.width
self.height = bitcell_1rw_1r.height
self.pin_map = bitcell_1rw_1r.pin_map
self.add_pin_types(self.type_list)
self.nets_match = self.do_nets_exist(self.storage_nets) self.nets_match = self.do_nets_exist(self.storage_nets)
pin_names = bitcell_1rw_1r.pin_names pin_names = self.pin_names
self.bl_names = [pin_names[0], pin_names[2]] self.bl_names = [pin_names[0], pin_names[2]]
self.br_names = [pin_names[1], pin_names[3]] self.br_names = [pin_names[1], pin_names[3]]
self.wl_names = [pin_names[4], pin_names[5]] self.wl_names = [pin_names[4], pin_names[5]]

21
compiler/bitcells/bitcell_1w_1r.py
View File

@ -6,10 +6,9 @@
# All rights reserved. # All rights reserved.
# #
import debug import debug
import utils
from tech import GDS, layer
from tech import cell_properties as props from tech import cell_properties as props
import bitcell_base import bitcell_base
from globals import OPTS
class bitcell_1w_1r(bitcell_base.bitcell_base): class bitcell_1w_1r(bitcell_base.bitcell_base):
@ -31,28 +30,20 @@ class bitcell_1w_1r(bitcell_base.bitcell_base):
type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT",
"INPUT", "INPUT", "POWER", "GROUND"] "INPUT", "INPUT", "POWER", "GROUND"]
storage_nets = ['Q', 'Q_bar'] storage_nets = ['Q', 'Q_bar']
(width, height) = utils.get_libcell_size("cell_1w_1r",
GDS["unit"],
layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "cell_1w_1r", GDS["unit"])
def __init__(self, name=""): def __init__(self, name, cell_name=None):
# Ignore the name argument if not cell_name:
bitcell_base.bitcell_base.__init__(self, "cell_1w_1r") cell_name = OPTS.bitcell_name
super().__init__(name, cell_name)
debug.info(2, "Create bitcell with 1W and 1R Port") debug.info(2, "Create bitcell with 1W and 1R Port")
self.width = bitcell_1w_1r.width
self.height = bitcell_1w_1r.height
self.pin_map = bitcell_1w_1r.pin_map
self.add_pin_types(self.type_list)
self.nets_match = self.do_nets_exist(self.storage_nets) self.nets_match = self.do_nets_exist(self.storage_nets)
pin_names = bitcell_1w_1r.pin_names pin_names = self.pin_names
self.bl_names = [pin_names[0], pin_names[2]] self.bl_names = [pin_names[0], pin_names[2]]
self.br_names = [pin_names[1], pin_names[3]] self.br_names = [pin_names[1], pin_names[3]]
self.wl_names = [pin_names[4], pin_names[5]] self.wl_names = [pin_names[4], pin_names[5]]
def get_bitcell_pins(self, col, row): def get_bitcell_pins(self, col, row):
""" """
Creates a list of connections in the bitcell, Creates a list of connections in the bitcell,

18
compiler/bitcells/bitcell_base.py
View File

@ -8,17 +8,29 @@
import debug import debug
import design import design
import utils
from globals import OPTS from globals import OPTS
import logical_effort import logical_effort
from tech import parameter, drc, layer from tech import GDS, parameter, drc, layer
class bitcell_base(design.design): class bitcell_base(design.design):
""" """
Base bitcell parameters to be over-riden. Base bitcell parameters to be over-riden.
""" """
def __init__(self, name): cell_size_layer = "boundary"
design.design.__init__(self, name)
def __init__(self, name, cell_name, hard_cell=True):
design.design.__init__(self, name, cell_name)
if hard_cell:
(self.width, self.height) = utils.get_libcell_size(cell_name,
GDS["unit"],
layer[self.cell_size_layer])
self.pin_map = utils.get_libcell_pins(self.pin_names,
cell_name,
GDS["unit"])
self.add_pin_types(self.type_list)
def get_stage_effort(self, load): def get_stage_effort(self, load):
parasitic_delay = 1 parasitic_delay = 1

20
compiler/bitcells/col_cap_bitcell_1rw_1r.py
View File

@ -6,8 +6,6 @@
# All rights reserved. # All rights reserved.
# #
import debug import debug
import utils
from tech import GDS, layer
from tech import cell_properties as props from tech import cell_properties as props
import bitcell_base import bitcell_base
@ -21,24 +19,14 @@ class col_cap_bitcell_1rw_1r(bitcell_base.bitcell_base):
props.bitcell.cell_1rw1r.pin.bl1, props.bitcell.cell_1rw1r.pin.bl1,
props.bitcell.cell_1rw1r.pin.br1, props.bitcell.cell_1rw1r.pin.br1,
props.bitcell.cell_1rw1r.pin.vdd] props.bitcell.cell_1rw1r.pin.vdd]
type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT",
"POWER", "GROUND"] "POWER", "GROUND"]
(width, height) = utils.get_libcell_size("col_cap_cell_1rw_1r", def __init__(self, name="col_cap_cell_1rw_1r", cell_name=None):
GDS["unit"], if not cell_name:
layer["boundary"]) cell_name = name
pin_map = utils.get_libcell_pins(pin_names,
"col_cap_cell_1rw_1r",
GDS["unit"])
def __init__(self, name=""):
# Ignore the name argument # Ignore the name argument
bitcell_base.bitcell_base.__init__(self, "col_cap_cell_1rw_1r") bitcell_base.bitcell_base.__init__(self, name, cell_name)
debug.info(2, "Create col_cap bitcell 1rw+1r object") debug.info(2, "Create col_cap bitcell 1rw+1r object")
self.width = col_cap_bitcell_1rw_1r.width
self.height = col_cap_bitcell_1rw_1r.height
self.pin_map = col_cap_bitcell_1rw_1r.pin_map
self.add_pin_types(self.type_list)
self.no_instances = True self.no_instances = True

20
compiler/bitcells/dummy_bitcell.py
View File

@ -6,10 +6,9 @@
# All rights reserved. # All rights reserved.
# #
import debug import debug
import utils
from tech import GDS, layer
from tech import cell_properties as props from tech import cell_properties as props
import bitcell_base import bitcell_base
from globals import OPTS
class dummy_bitcell(bitcell_base.bitcell_base): class dummy_bitcell(bitcell_base.bitcell_base):
@ -24,19 +23,12 @@ class dummy_bitcell(bitcell_base.bitcell_base):
props.bitcell.cell_6t.pin.wl, props.bitcell.cell_6t.pin.wl,
props.bitcell.cell_6t.pin.vdd, props.bitcell.cell_6t.pin.vdd,
props.bitcell.cell_6t.pin.gnd] props.bitcell.cell_6t.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
(width, height) = utils.get_libcell_size("dummy_cell_6t", def __init__(self, name, cell_name=None):
GDS["unit"], if not cell_name:
layer["boundary"]) cell_name = OPTS.dummy_bitcell_name
pin_map = utils.get_libcell_pins(pin_names, "dummy_cell_6t", GDS["unit"]) super().__init__(name, cell_name)
def __init__(self, name=""):
# Ignore the name argument
bitcell_base.bitcell_base.__init__(self, "dummy_cell_6t")
debug.info(2, "Create dummy bitcell") debug.info(2, "Create dummy bitcell")
self.width = dummy_bitcell.width
self.height = dummy_bitcell.height
self.pin_map = dummy_bitcell.pin_map

21
compiler/bitcells/dummy_bitcell_1rw_1r.py
View File

@ -6,10 +6,9 @@
# All rights reserved. # All rights reserved.
# #
import debug import debug
import utils
from tech import GDS, layer
from tech import cell_properties as props from tech import cell_properties as props
import bitcell_base import bitcell_base
from globals import OPTS
class dummy_bitcell_1rw_1r(bitcell_base.bitcell_base): class dummy_bitcell_1rw_1r(bitcell_base.bitcell_base):
@ -27,23 +26,13 @@ class dummy_bitcell_1rw_1r(bitcell_base.bitcell_base):
props.bitcell.cell_1rw1r.pin.wl1, props.bitcell.cell_1rw1r.pin.wl1,
props.bitcell.cell_1rw1r.pin.vdd, props.bitcell.cell_1rw1r.pin.vdd,
props.bitcell.cell_1rw1r.pin.gnd] props.bitcell.cell_1rw1r.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT",
"INPUT", "INPUT", "POWER", "GROUND"] "INPUT", "INPUT", "POWER", "GROUND"]
(width, height) = utils.get_libcell_size("dummy_cell_1rw_1r",
GDS["unit"],
layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names,
"dummy_cell_1rw_1r",
GDS["unit"])
def __init__(self, name=""): def __init__(self, name, cell_name=None):
# Ignore the name argument if not cell_name:
bitcell_base.bitcell_base.__init__(self, "dummy_cell_1rw_1r") cell_name = OPTS.dummy_bitcell_name
super().__init__(name, cell_name)
debug.info(2, "Create dummy bitcell 1rw+1r object") debug.info(2, "Create dummy bitcell 1rw+1r object")
self.width = dummy_bitcell_1rw_1r.width
self.height = dummy_bitcell_1rw_1r.height
self.pin_map = dummy_bitcell_1rw_1r.pin_map
self.add_pin_types(self.type_list)

21
compiler/bitcells/dummy_bitcell_1w_1r.py
View File

@ -6,10 +6,9 @@
# All rights reserved. # All rights reserved.
# #
import debug import debug
import utils
from tech import GDS, layer
from tech import cell_properties as props from tech import cell_properties as props
import bitcell_base import bitcell_base
from globals import OPTS
class dummy_bitcell_1w_1r(bitcell_base.bitcell_base): class dummy_bitcell_1w_1r(bitcell_base.bitcell_base):
@ -29,21 +28,13 @@ class dummy_bitcell_1w_1r(bitcell_base.bitcell_base):
props.bitcell.cell_1w1r.pin.gnd] props.bitcell.cell_1w1r.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT",
"INPUT", "INPUT", "POWER", "GROUND"] "INPUT", "INPUT", "POWER", "GROUND"]
(width, height) = utils.get_libcell_size("dummy_cell_1w_1r",
GDS["unit"],
layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names,
"dummy_cell_1w_1r",
GDS["unit"])
def __init__(self, name=""): def __init__(self, name, cell_name=None):
# Ignore the name argument if not cell_name:
bitcell_base.bitcell_base.__init__(self, "dummy_cell_1w_1r") cell_name = OPTS.dummy_bitcell_name
super().__init__(name, cell_name)
debug.info(2, "Create dummy bitcell 1w+1r object") debug.info(2, "Create dummy bitcell 1w+1r object")
self.width = dummy_bitcell_1w_1r.width
self.height = dummy_bitcell_1w_1r.height
self.pin_map = dummy_bitcell_1w_1r.pin_map
self.add_pin_types(self.type_list)

13
compiler/bitcells/dummy_pbitcell.py
View File

@ -7,23 +7,25 @@
# #
import debug import debug
import design import design
from tech import drc, spice,parameter
from vector import vector from vector import vector
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
class dummy_pbitcell(design.design): class dummy_pbitcell(design.design):
""" """
Creates a replica bitcell using pbitcell Creates a replica bitcell using pbitcell
""" """
def __init__(self, name): def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = name
self.num_rw_ports = OPTS.num_rw_ports self.num_rw_ports = OPTS.num_rw_ports
self.num_w_ports = OPTS.num_w_ports self.num_w_ports = OPTS.num_w_ports
self.num_r_ports = OPTS.num_r_ports self.num_r_ports = OPTS.num_r_ports
self.total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports self.total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports
design.design.__init__(self, name) design.design.__init__(self, name, cell_name)
debug.info(1, "create a dummy bitcell using pbitcell with {0} rw ports, {1} w ports and {2} r ports".format(self.num_rw_ports, debug.info(1, "create a dummy bitcell using pbitcell with {0} rw ports, {1} w ports and {2} r ports".format(self.num_rw_ports,
self.num_w_ports, self.num_w_ports,
self.num_r_ports)) self.num_r_ports))
@ -54,7 +56,8 @@ class dummy_pbitcell(design.design):
self.add_pin("gnd") self.add_pin("gnd")
def add_modules(self): def add_modules(self):
self.prbc = factory.create(module_type="pbitcell",dummy_bitcell=True) self.prbc = factory.create(module_type="pbitcell",
dummy_bitcell=True)
self.add_mod(self.prbc) self.add_mod(self.prbc)
self.height = self.prbc.height self.height = self.prbc.height
@ -75,7 +78,7 @@ class dummy_pbitcell(design.design):
self.connect_inst(temp) self.connect_inst(temp)
def place_pbitcell(self): def place_pbitcell(self):
self.prbc_inst.place(offset=vector(0,0)) self.prbc_inst.place(offset=vector(0, 0))
def route_rbc_connections(self): def route_rbc_connections(self):
for port in range(self.total_ports): for port in range(self.total_ports):

6
compiler/bitcells/pbitcell.py
View File

@ -21,7 +21,9 @@ class pbitcell(bitcell_base.bitcell_base):
with a variable number of read/write, write, and read ports with a variable number of read/write, write, and read ports
""" """
def __init__(self, name, replica_bitcell=False, dummy_bitcell=False): def __init__(self, name, cell_name=None, replica_bitcell=False, dummy_bitcell=False):
if not cell_name:
cell_name = name
self.num_rw_ports = OPTS.num_rw_ports self.num_rw_ports = OPTS.num_rw_ports
self.num_w_ports = OPTS.num_w_ports self.num_w_ports = OPTS.num_w_ports
self.num_r_ports = OPTS.num_r_ports self.num_r_ports = OPTS.num_r_ports
@ -30,7 +32,7 @@ class pbitcell(bitcell_base.bitcell_base):
self.replica_bitcell = replica_bitcell self.replica_bitcell = replica_bitcell
self.dummy_bitcell = dummy_bitcell self.dummy_bitcell = dummy_bitcell
bitcell_base.bitcell_base.__init__(self, name) bitcell_base.bitcell_base.__init__(self, name, cell_name, hard_cell=False)
fmt_str = "{0} rw ports, {1} w ports and {2} r ports" fmt_str = "{0} rw ports, {1} w ports and {2} r ports"
info_string = fmt_str.format(self.num_rw_ports, info_string = fmt_str.format(self.num_rw_ports,
self.num_w_ports, self.num_w_ports,

26
compiler/bitcells/replica_bitcell.py
View File

@ -5,15 +5,15 @@
# (acting for and on behalf of Oklahoma State University) # (acting for and on behalf of Oklahoma State University)
# All rights reserved. # All rights reserved.
# #
import design
import debug import debug
import utils import utils
from tech import GDS,layer,drc,parameter,cell_properties import bitcell_base
from tech import GDS, layer
from tech import cell_properties as props from tech import cell_properties as props
from globals import OPTS from globals import OPTS
class replica_bitcell(design.design):
class replica_bitcell(bitcell_base.bitcell_base):
""" """
A single bit cell (6T, 8T, etc.) A single bit cell (6T, 8T, etc.)
This module implements the single memory cell used in the design. It This module implements the single memory cell used in the design. It
@ -27,23 +27,13 @@ class replica_bitcell(design.design):
props.bitcell.cell_6t.pin.gnd] props.bitcell.cell_6t.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] type_list = ["OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
if not OPTS.netlist_only: def __init__(self, name, cell_name=None):
(width,height) = utils.get_libcell_size("replica_cell_6t", GDS["unit"], layer["boundary"]) if not cell_name:
pin_map = utils.get_libcell_pins(pin_names, "replica_cell_6t", GDS["unit"]) cell_name = OPTS.replica_bitcell_name
else:
(width,height) = (0,0)
pin_map = []
def __init__(self, name=""):
# Ignore the name argument # Ignore the name argument
design.design.__init__(self, "replica_cell_6t") super().__init__(name, cell_name)
debug.info(2, "Create replica bitcell object") debug.info(2, "Create replica bitcell object")
self.width = replica_bitcell.width
self.height = replica_bitcell.height
self.pin_map = replica_bitcell.pin_map
self.add_pin_types(self.type_list)
def get_stage_effort(self, load): def get_stage_effort(self, load):
parasitic_delay = 1 parasitic_delay = 1
size = 0.5 #This accounts for bitline being drained thought the access TX and internal node size = 0.5 #This accounts for bitline being drained thought the access TX and internal node

23
compiler/bitcells/replica_bitcell_1rw_1r.py
View File

@ -5,13 +5,13 @@
# (acting for and on behalf of Oklahoma State University) # (acting for and on behalf of Oklahoma State University)
# All rights reserved. # All rights reserved.
# #
import design
import debug import debug
import utils import bitcell_base
from tech import GDS,layer,drc,parameter
from tech import cell_properties as props from tech import cell_properties as props
from globals import OPTS
class replica_bitcell_1rw_1r(design.design):
class replica_bitcell_1rw_1r(bitcell_base.bitcell_base):
""" """
A single bit cell which is forced to store a 0. A single bit cell which is forced to store a 0.
This module implements the single memory cell used in the design. It This module implements the single memory cell used in the design. It
@ -26,21 +26,14 @@ class replica_bitcell_1rw_1r(design.design):
props.bitcell.cell_1rw1r.pin.wl1, props.bitcell.cell_1rw1r.pin.wl1,
props.bitcell.cell_1rw1r.pin.vdd, props.bitcell.cell_1rw1r.pin.vdd,
props.bitcell.cell_1rw1r.pin.gnd] props.bitcell.cell_1rw1r.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"] type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]
(width,height) = utils.get_libcell_size("replica_cell_1rw_1r", GDS["unit"], layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "replica_cell_1rw_1r", GDS["unit"])
def __init__(self, name=""): def __init__(self, name, cell_name=None):
# Ignore the name argument if not cell_name:
design.design.__init__(self, "replica_cell_1rw_1r") cell_name = OPTS.replica_bitcell_name
super().__init__(name, cell_name)
debug.info(2, "Create replica bitcell 1rw+1r object") debug.info(2, "Create replica bitcell 1rw+1r object")
self.width = replica_bitcell_1rw_1r.width
self.height = replica_bitcell_1rw_1r.height
self.pin_map = replica_bitcell_1rw_1r.pin_map
self.add_pin_types(self.type_list)
def get_stage_effort(self, load): def get_stage_effort(self, load):
parasitic_delay = 1 parasitic_delay = 1
size = 0.5 #This accounts for bitline being drained thought the access TX and internal node size = 0.5 #This accounts for bitline being drained thought the access TX and internal node

24
compiler/bitcells/replica_bitcell_1w_1r.py
View File

@ -5,13 +5,15 @@
# (acting for and on behalf of Oklahoma State University) # (acting for and on behalf of Oklahoma State University)
# All rights reserved. # All rights reserved.
# #
import design
import debug import debug
import utils import bitcell_base
from tech import GDS,layer,drc,parameter
from tech import cell_properties as props from tech import cell_properties as props
from globals import OPTS
from tech import GDS, layer
import utils
class replica_bitcell_1w_1r(design.design):
class replica_bitcell_1w_1r(bitcell_base.bitcell_base):
""" """
A single bit cell which is forced to store a 0. A single bit cell which is forced to store a 0.
This module implements the single memory cell used in the design. It This module implements the single memory cell used in the design. It
@ -26,20 +28,14 @@ class replica_bitcell_1w_1r(design.design):
props.bitcell.cell_1w1r.pin.wl1, props.bitcell.cell_1w1r.pin.wl1,
props.bitcell.cell_1w1r.pin.vdd, props.bitcell.cell_1w1r.pin.vdd,
props.bitcell.cell_1w1r.pin.gnd] props.bitcell.cell_1w1r.pin.gnd]
type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "INPUT", "INPUT", "POWER", "GROUND"] type_list = ["OUTPUT", "OUTPUT", "INPUT", "INPUT", "INPUT", "INPUT", "POWER", "GROUND"]
(width,height) = utils.get_libcell_size("replica_cell_1w_1r", GDS["unit"], layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "replica_cell_1w_1r", GDS["unit"])
def __init__(self, name=""): def __init__(self, name, cell_name=None):
# Ignore the name argument if not cell_name:
design.design.__init__(self, "replica_cell_1w_1r") cell_name = OPTS.replica_bitcell_name
super().__init__(name, cell_name)
debug.info(2, "Create replica bitcell 1w+1r object") debug.info(2, "Create replica bitcell 1w+1r object")
self.width = replica_bitcell_1w_1r.width
self.height = replica_bitcell_1w_1r.height
self.pin_map = replica_bitcell_1w_1r.pin_map
self.add_pin_types(self.type_list)
def get_stage_effort(self, load): def get_stage_effort(self, load):
parasitic_delay = 1 parasitic_delay = 1

13
compiler/bitcells/replica_pbitcell.py
View File

@ -7,23 +7,25 @@
# #
import debug import debug
import design import design
from tech import drc, spice,parameter
from vector import vector from vector import vector
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
class replica_pbitcell(design.design): class replica_pbitcell(design.design):
""" """
Creates a replica bitcell using pbitcell Creates a replica bitcell using pbitcell
""" """
def __init__(self, name): def __init__(self, name, cell_name=None):
if not cell_name:
cell_name = name
self.num_rw_ports = OPTS.num_rw_ports self.num_rw_ports = OPTS.num_rw_ports
self.num_w_ports = OPTS.num_w_ports self.num_w_ports = OPTS.num_w_ports
self.num_r_ports = OPTS.num_r_ports self.num_r_ports = OPTS.num_r_ports
self.total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports self.total_ports = self.num_rw_ports + self.num_w_ports + self.num_r_ports
design.design.__init__(self, name) design.design.__init__(self, name, cell_name)
debug.info(1, "create a replica bitcell using pbitcell with {0} rw ports, {1} w ports and {2} r ports".format(self.num_rw_ports, debug.info(1, "create a replica bitcell using pbitcell with {0} rw ports, {1} w ports and {2} r ports".format(self.num_rw_ports,
self.num_w_ports, self.num_w_ports,
self.num_r_ports)) self.num_r_ports))
@ -54,7 +56,8 @@ class replica_pbitcell(design.design):
self.add_pin("gnd") self.add_pin("gnd")
def add_modules(self): def add_modules(self):
self.prbc = factory.create(module_type="pbitcell",replica_bitcell=True) self.prbc = factory.create(module_type="pbitcell",
replica_bitcell=True)
self.add_mod(self.prbc) self.add_mod(self.prbc)
self.height = self.prbc.height self.height = self.prbc.height
@ -75,7 +78,7 @@ class replica_pbitcell(design.design):
self.connect_inst(temp) self.connect_inst(temp)
def place_pbitcell(self): def place_pbitcell(self):
self.prbc_inst.place(offset=vector(0,0)) self.prbc_inst.place(offset=vector(0, 0))
def route_rbc_connections(self): def route_rbc_connections(self):
for port in range(self.total_ports): for port in range(self.total_ports):

21
compiler/bitcells/row_cap_bitcell_1rw_1r.py
View File

@ -6,8 +6,6 @@
# All rights reserved. # All rights reserved.
# #
import debug import debug
import utils
from tech import GDS, layer
from tech import cell_properties as props from tech import cell_properties as props
import bitcell_base import bitcell_base
@ -22,23 +20,12 @@ class row_cap_bitcell_1rw_1r(bitcell_base.bitcell_base):
pin_names = [props.bitcell.cell_1rw1r.pin.wl0, pin_names = [props.bitcell.cell_1rw1r.pin.wl0,
props.bitcell.cell_1rw1r.pin.wl1, props.bitcell.cell_1rw1r.pin.wl1,
props.bitcell.cell_1rw1r.pin.gnd] props.bitcell.cell_1rw1r.pin.gnd]
type_list = ["INPUT", "INPUT", "GROUND"] type_list = ["INPUT", "INPUT", "GROUND"]
(width, height) = utils.get_libcell_size("row_cap_cell_1rw_1r", def __init__(self, name="row_cap_cell_1rw_1r", cell_name=None):
GDS["unit"], if not cell_name:
layer["boundary"]) cell_name = name
pin_map = utils.get_libcell_pins(pin_names, bitcell_base.bitcell_base.__init__(self, name, cell_name)
"row_cap_cell_1rw_1r",
GDS["unit"])
def __init__(self, name=""):
# Ignore the name argument
bitcell_base.bitcell_base.__init__(self, "row_cap_cell_1rw_1r")
debug.info(2, "Create row_cap bitcell 1rw+1r object") debug.info(2, "Create row_cap bitcell 1rw+1r object")
self.width = row_cap_bitcell_1rw_1r.width
self.height = row_cap_bitcell_1rw_1r.height
self.pin_map = row_cap_bitcell_1rw_1r.pin_map
self.add_pin_types(self.type_list)
self.no_instances = True self.no_instances = True

25
compiler/custom/dff.py
View File

@ -6,7 +6,7 @@
# All rights reserved. # All rights reserved.
# #
import design import design
from tech import GDS, layer, spice, parameter from tech import GDS, layer, spice
from tech import cell_properties as props from tech import cell_properties as props
import utils import utils
@ -23,18 +23,22 @@ class dff(design.design):
pin_names = props.dff.custom_port_list pin_names = props.dff.custom_port_list
type_list = props.dff.custom_type_list type_list = props.dff.custom_type_list
clk_pin = props.dff.clk_pin clk_pin = props.dff.clk_pin
cell_size_layer = "boundary"
(width, height) = utils.get_libcell_size("dff",
GDS["unit"],
layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "dff", GDS["unit"])
def __init__(self, name="dff"): def __init__(self, name="dff"):
design.design.__init__(self, name) super().__init__(name)
self.width = dff.width (width, height) = utils.get_libcell_size(self.cell_name,
self.height = dff.height GDS["unit"],
self.pin_map = dff.pin_map layer[self.cell_size_layer])
pin_map = utils.get_libcell_pins(self.pin_names,
self.cell_name,
GDS["unit"])
self.width = width
self.height = height
self.pin_map = pin_map
self.add_pin_types(self.type_list) self.add_pin_types(self.type_list)
def analytical_power(self, corner, load): def analytical_power(self, corner, load):
@ -49,7 +53,6 @@ class dff(design.design):
def calculate_effective_capacitance(self, load): def calculate_effective_capacitance(self, load):
"""Computes effective capacitance. Results in fF""" """Computes effective capacitance. Results in fF"""
from tech import parameter
c_load = load c_load = load
c_para = spice["dff_out_cap"]#ff c_para = spice["dff_out_cap"]#ff
transition_prob = 0.5 transition_prob = 0.5

23
compiler/custom/inv_dec.py
View File

@ -9,7 +9,6 @@ import design
from tech import GDS, layer, spice, parameter from tech import GDS, layer, spice, parameter
import logical_effort import logical_effort
import utils import utils
import debug
class inv_dec(design.design): class inv_dec(design.design):
@ -19,18 +18,22 @@ class inv_dec(design.design):
pin_names = ["A", "Z", "vdd", "gnd"] pin_names = ["A", "Z", "vdd", "gnd"]
type_list = ["INPUT", "OUTPUT", "POWER", "GROUND"] type_list = ["INPUT", "OUTPUT", "POWER", "GROUND"]
cell_size_layer = "boundary"
(width, height) = utils.get_libcell_size("inv_dec",
GDS["unit"],
layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "inv_dec", GDS["unit"])
def __init__(self, name="inv_dec", height=None): def __init__(self, name="inv_dec", height=None):
design.design.__init__(self, name) super().__init__(name)
self.width = inv_dec.width (width, height) = utils.get_libcell_size(self.cell_name,
self.height = inv_dec.height GDS["unit"],
self.pin_map = inv_dec.pin_map layer[self.cell_size_layer])
pin_map = utils.get_libcell_pins(self.pin_names,
self.cell_name,
GDS["unit"])
self.width = width
self.height = height
self.pin_map = pin_map
self.add_pin_types(self.type_list) self.add_pin_types(self.type_list)
def analytical_power(self, corner, load): def analytical_power(self, corner, load):

22
compiler/custom/nand2_dec.py
View File

@ -18,18 +18,22 @@ class nand2_dec(design.design):
pin_names = ["A", "B", "Z", "vdd", "gnd"] pin_names = ["A", "B", "Z", "vdd", "gnd"]
type_list = ["INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"] type_list = ["INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"]
cell_size_layer = "boundary"
(width, height) = utils.get_libcell_size("nand2_dec",
GDS["unit"],
layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "nand2_dec", GDS["unit"])
def __init__(self, name="nand2_dec", height=None): def __init__(self, name="nand2_dec", height=None):
design.design.__init__(self, name) super().__init__(name)
self.width = nand2_dec.width (width, height) = utils.get_libcell_size(self.cell_name,
self.height = nand2_dec.height GDS["unit"],
self.pin_map = nand2_dec.pin_map layer[self.cell_size_layer])
pin_map = utils.get_libcell_pins(self.pin_names,
self.cell_name,
GDS["unit"])
self.width = width
self.height = height
self.pin_map = pin_map
self.add_pin_types(self.type_list) self.add_pin_types(self.type_list)
# FIXME: For now... # FIXME: For now...

22
compiler/custom/nand3_dec.py
View File

@ -18,18 +18,22 @@ class nand3_dec(design.design):
pin_names = ["A", "B", "C", "Z", "vdd", "gnd"] pin_names = ["A", "B", "C", "Z", "vdd", "gnd"]
type_list = ["INPUT", "INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"] type_list = ["INPUT", "INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"]
cell_size_layer = "boundary"
(width, height) = utils.get_libcell_size("nand3_dec",
GDS["unit"],
layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "nand3_dec", GDS["unit"])
def __init__(self, name="nand3_dec", height=None): def __init__(self, name="nand3_dec", height=None):
design.design.__init__(self, name) super().__init__(name)
self.width = nand3_dec.width (width, height) = utils.get_libcell_size(self.cell_name,
self.height = nand3_dec.height GDS["unit"],
self.pin_map = nand3_dec.pin_map layer[self.cell_size_layer])
pin_map = utils.get_libcell_pins(self.pin_names,
self.cell_name,
GDS["unit"])
self.width = width
self.height = height
self.pin_map = pin_map
self.add_pin_types(self.type_list) self.add_pin_types(self.type_list)
# FIXME: For now... # FIXME: For now...

22
compiler/custom/nand4_dec.py
View File

@ -18,18 +18,22 @@ class nand4_dec(design.design):
pin_names = ["A", "B", "C", "D", "Z", "vdd", "gnd"] pin_names = ["A", "B", "C", "D", "Z", "vdd", "gnd"]
type_list = ["INPUT", "INPUT", "INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"] type_list = ["INPUT", "INPUT", "INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"]
cell_size_layer = "boundary"
(width, height) = utils.get_libcell_size("nand4_dec",
GDS["unit"],
layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "nand4_dec", GDS["unit"])
def __init__(self, name="nand4_dec", height=None): def __init__(self, name="nand4_dec", height=None):
design.design.__init__(self, name) super().__init__(name)
self.width = nand4_dec.width (width, height) = utils.get_libcell_size(self.cell_name,
self.height = nand4_dec.height GDS["unit"],
self.pin_map = nand4_dec.pin_map layer[self.cell_size_layer])
pin_map = utils.get_libcell_pins(self.pin_names,
self.cell_name,
GDS["unit"])
self.width = width
self.height = height
self.pin_map = pin_map
self.add_pin_types(self.type_list) self.add_pin_types(self.type_list)
# FIXME: For now... # FIXME: For now...

34
compiler/modules/sense_amp.py → compiler/custom/sense_amp.py
View File

@ -10,7 +10,6 @@ import debug
import utils import utils
from tech import GDS, layer, parameter, drc from tech import GDS, layer, parameter, drc
from tech import cell_properties as props from tech import cell_properties as props
from globals import OPTS
import logical_effort import logical_effort
@ -28,12 +27,24 @@ class sense_amp(design.design):
props.sense_amp.pin.vdd, props.sense_amp.pin.vdd,
props.sense_amp.pin.gnd] props.sense_amp.pin.gnd]
type_list = ["INPUT", "INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] type_list = ["INPUT", "INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
if not OPTS.netlist_only: cell_size_layer = "boundary"
(width, height) = utils.get_libcell_size("sense_amp", GDS["unit"], layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "sense_amp", GDS["unit"]) def __init__(self, name="sense_amp"):
else: super().__init__(name)
(width, height) = (0, 0) debug.info(2, "Create sense_amp")
pin_map = []
(width, height) = utils.get_libcell_size(self.cell_name,
GDS["unit"],
layer[self.cell_size_layer])
pin_map = utils.get_libcell_pins(self.pin_names,
self.cell_name,
GDS["unit"])
self.width = width
self.height = height
self.pin_map = pin_map
self.add_pin_types(self.type_list)
def get_bl_names(self): def get_bl_names(self):
return props.sense_amp.pin.bl return props.sense_amp.pin.bl
@ -49,15 +60,6 @@ class sense_amp(design.design):
def en_name(self): def en_name(self):
return props.sense_amp.pin.en return props.sense_amp.pin.en
def __init__(self, name):
super().__init__(name)
debug.info(2, "Create sense_amp")
self.width = sense_amp.width
self.height = sense_amp.height
self.pin_map = sense_amp.pin_map
self.add_pin_types(self.type_list)
def get_cin(self): def get_cin(self):
# FIXME: This input load will be applied to both the s_en timing and bitline timing. # FIXME: This input load will be applied to both the s_en timing and bitline timing.

22
compiler/custom/tri_gate.py
View File

@ -8,7 +8,8 @@
import debug import debug
import design import design
import utils import utils
from tech import GDS,layer from tech import GDS, layer
class tri_gate(design.design): class tri_gate(design.design):
""" """
@ -19,8 +20,7 @@ class tri_gate(design.design):
pin_names = ["in", "out", "en", "en_bar", "vdd", "gnd"] pin_names = ["in", "out", "en", "en_bar", "vdd", "gnd"]
type_list = ["INPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"] type_list = ["INPUT", "OUTPUT", "INPUT", "INPUT", "POWER", "GROUND"]
(width,height) = utils.get_libcell_size("tri_gate", GDS["unit"], layer["boundary"]) cell_size_layer = "boundary"
pin_map = utils.get_libcell_pins(pin_names, "tri_gate", GDS["unit"])
unique_id = 1 unique_id = 1
@ -28,12 +28,20 @@ class tri_gate(design.design):
if name=="": if name=="":
name = "tri{0}".format(tri_gate.unique_id) name = "tri{0}".format(tri_gate.unique_id)
tri_gate.unique_id += 1 tri_gate.unique_id += 1
design.design.__init__(self, name) super().__init__(self, name)
debug.info(2, "Create tri_gate") debug.info(2, "Create tri_gate")
self.width = tri_gate.width (width, height) = utils.get_libcell_size(self.cell_name,
self.height = tri_gate.height GDS["unit"],
self.pin_map = tri_gate.pin_map layer[self.cell_size_layer])
pin_map = utils.get_libcell_pins(self.pin_names,
self.cell_name,
GDS["unit"])
self.width = width
self.height = height
self.pin_map = pin_map
self.add_pin_types(self.type_list) self.add_pin_types(self.type_list)
def analytical_power(self, corner, load): def analytical_power(self, corner, load):

27
compiler/custom/write_driver.py
View File

@ -8,10 +8,10 @@
import debug import debug
import design import design
import utils import utils
from globals import OPTS from tech import GDS, layer
from tech import GDS,layer
from tech import cell_properties as props from tech import cell_properties as props
class write_driver(design.design): class write_driver(design.design):
""" """
Tristate write driver to be active during write operations only. Tristate write driver to be active during write operations only.
@ -28,20 +28,23 @@ class write_driver(design.design):
props.write_driver.pin.gnd] props.write_driver.pin.gnd]
type_list = ["INPUT", "OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] type_list = ["INPUT", "OUTPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
if not OPTS.netlist_only: cell_size_layer = "boundary"
(width,height) = utils.get_libcell_size("write_driver", GDS["unit"], layer["boundary"])
pin_map = utils.get_libcell_pins(pin_names, "write_driver", GDS["unit"])
else:
(width,height) = (0,0)
pin_map = []
def __init__(self, name): def __init__(self, name):
design.design.__init__(self, name) super().__init__(name)
debug.info(2, "Create write_driver") debug.info(2, "Create write_driver")
self.width = write_driver.width (width, height) = utils.get_libcell_size(self.cell_name,
self.height = write_driver.height GDS["unit"],
self.pin_map = write_driver.pin_map layer[self.cell_size_layer])
pin_map = utils.get_libcell_pins(self.pin_names,
self.cell_name,
GDS["unit"])
self.width = width
self.height = height
self.pin_map = pin_map
self.add_pin_types(self.type_list) self.add_pin_types(self.type_list)
def get_bl_names(self): def get_bl_names(self):

27
compiler/globals.py
View File

@ -189,6 +189,9 @@ def init_openram(config_file, is_unit_test=True):
OPTS.__dict__ = CHECKPOINT_OPTS.__dict__.copy() OPTS.__dict__ = CHECKPOINT_OPTS.__dict__.copy()
return return
# Setup correct bitcell names
setup_bitcell()
# Import these to find the executables for checkpointing # Import these to find the executables for checkpointing
import characterizer import characterizer
import verify import verify
@ -202,8 +205,6 @@ def setup_bitcell():
""" """
Determine the correct custom or parameterized bitcell for the design. Determine the correct custom or parameterized bitcell for the design.
""" """
global OPTS
# If we have non-1rw ports, # If we have non-1rw ports,
# and the user didn't over-ride the bitcell manually, # and the user didn't over-ride the bitcell manually,
# figure out the right bitcell to use # figure out the right bitcell to use
@ -211,8 +212,7 @@ def setup_bitcell():
if (OPTS.num_rw_ports == 1 and OPTS.num_w_ports == 0 and OPTS.num_r_ports == 0): if (OPTS.num_rw_ports == 1 and OPTS.num_w_ports == 0 and OPTS.num_r_ports == 0):
OPTS.bitcell = "bitcell" OPTS.bitcell = "bitcell"
OPTS.replica_bitcell = "replica_bitcell" OPTS.bitcell_name = "cell_6t"
OPTS.dummy_bitcell = "dummy_bitcell"
else: else:
ports = "" ports = ""
if OPTS.num_rw_ports > 0: if OPTS.num_rw_ports > 0:
@ -225,6 +225,20 @@ def setup_bitcell():
if ports != "": if ports != "":
OPTS.bitcell_suffix = "_" + ports OPTS.bitcell_suffix = "_" + ports
OPTS.bitcell = "bitcell" + OPTS.bitcell_suffix OPTS.bitcell = "bitcell" + OPTS.bitcell_suffix
OPTS.bitcell_name = "cell" + OPTS.bitcell_suffix
OPTS.dummy_bitcell = "dummy_" + OPTS.bitcell
OPTS.dummy_bitcell_name = "dummy_" + OPTS.bitcell_name
OPTS.replica_bitcell = "replica_" + OPTS.bitcell
OPTS.replica_bitcell_name = "replica_" + OPTS.bitcell_name
elif (OPTS.bitcell == "pbitcell"):
OPTS.bitcell = "pbitcell"
OPTS.bitcell_name = "pbitcell"
OPTS.dummy_bitcell = "dummy_pbitcell"
OPTS.dummy_bitcell_name = "dummy_pbitcell"
OPTS.replica_bitcell = "replica_pbitcell"
OPTS.replica_bitcell_name = "replica_pbitcell"
# See if bitcell exists # See if bitcell exists
try: try:
@ -234,6 +248,11 @@ def setup_bitcell():
# or its custom replica bitcell # or its custom replica bitcell
# Use the pbitcell (and give a warning if not in unit test mode) # Use the pbitcell (and give a warning if not in unit test mode)
OPTS.bitcell = "pbitcell" OPTS.bitcell = "pbitcell"
OPTS.bitcell_name = "pbitcell"
OPTS.dummy_bitcell = "dummy_pbitcell"
OPTS.dummy_bitcell_name = "dummy_pbitcell"
OPTS.replica_bitcell = "replica_pbitcell"
OPTS.replica_bitcell_name = "replica_pbitcell"
if not OPTS.is_unit_test: if not OPTS.is_unit_test:
debug.warning("Using the parameterized bitcell which may have suboptimal density.") debug.warning("Using the parameterized bitcell which may have suboptimal density.")
debug.info(1, "Using bitcell: {}".format(OPTS.bitcell)) debug.info(1, "Using bitcell: {}".format(OPTS.bitcell))

0
compiler/custom/and2_dec.py → compiler/modules/and2_dec.py
View File

0
compiler/custom/and3_dec.py → compiler/modules/and3_dec.py
View File

0
compiler/custom/and4_dec.py → compiler/modules/and4_dec.py
View File

271
compiler/modules/custom_cell.py
View File

@ -1,271 +0,0 @@
# See LICENSE for licensing information.
#
# Copyright (c) 2016-2019 Regents of the University of California and The Board
# of Regents for the Oklahoma Agricultural and Mechanical College
# (acting for and on behalf of Oklahoma State University)
# All rights reserved.
#
import design
import debug
from tech import drc
from sram_factory import factory
from vector import vector
from globals import OPTS
class custom_cell(design.design):
"""
Array of tristate drivers to write to the bitlines through the column mux.
Dynamically generated write driver array of all bitlines.
"""
def __init__(self, name, pins, mod):
design.design.__init__(self, name)
debug.info(1, "Creating {0}".format(self.name))
self.add_comment("columns: {0}".format(columns))
self.add_comment("word_size {0}".format(word_size))
self.columns = columns
self.word_size = word_size
self.write_size = write_size
self.column_offset = column_offset
self.words_per_row = int(columns / word_size)
if not num_spare_cols:
self.num_spare_cols = 0
else:
self.num_spare_cols = num_spare_cols
if self.write_size:
self.num_wmasks = int(self.word_size / self.write_size)
self.create_netlist()
if not OPTS.netlist_only:
self.create_layout()
def get_bl_name(self):
bl_name = "bl"
return bl_name
def get_br_name(self):
br_name = "br"
return br_name
@property
def data_name(self):
return "data"
@property
def en_name(self):
return "en"
def create_netlist(self):
self.add_modules()
self.add_pins()
self.create_write_array()
def create_layout(self):
if self.bitcell.width > self.driver.width:
self.width = (self.columns + self.num_spare_cols) * self.bitcell.width
self.width_regular_cols = self.columns * self.bitcell.width
self.single_col_width = self.bitcell.width
else:
self.width = (self.columns + self.num_spare_cols) * self.driver.width
self.width_regular_cols = self.columns * self.driver.width
self.single_col_width = self.driver.width
self.height = self.driver.height
self.place_write_array()
self.add_layout_pins()
self.add_boundary()
self.DRC_LVS()
def add_pins(self):
for i in range(self.word_size + self.num_spare_cols):
self.add_pin(self.data_name + "_{0}".format(i), "INPUT")
for i in range(self.word_size + self.num_spare_cols):
self.add_pin(self.get_bl_name() + "_{0}".format(i), "OUTPUT")
self.add_pin(self.get_br_name() + "_{0}".format(i), "OUTPUT")
if self.write_size:
for i in range(self.num_wmasks + self.num_spare_cols):
self.add_pin(self.en_name + "_{0}".format(i), "INPUT")
elif self.num_spare_cols and not self.write_size:
for i in range(self.num_spare_cols + 1):
self.add_pin(self.en_name + "_{0}".format(i), "INPUT")
else:
self.add_pin(self.en_name, "INPUT")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
def add_modules(self):
self.driver = factory.create(module_type="write_driver")
self.add_mod(self.driver)
# This is just used for measurements,
# so don't add the module
self.bitcell = factory.create(module_type="bitcell")
def create_write_array(self):
self.driver_insts = {}
w = 0
windex=0
for i in range(0, self.columns, self.words_per_row):
name = "write_driver{}".format(i)
index = int(i / self.words_per_row)
self.driver_insts[index]=self.add_inst(name=name,
mod=self.driver)
if self.write_size:
self.connect_inst([self.data_name + "_{0}".format(index),
self.get_bl_name() + "_{0}".format(index),
self.get_br_name() + "_{0}".format(index),
self.en_name + "_{0}".format(windex), "vdd", "gnd"])
w+=1
# when w equals write size, the next en pin can be connected since we are now at the next wmask bit
if w == self.write_size:
w = 0
windex+=1
elif self.num_spare_cols and not self.write_size:
self.connect_inst([self.data_name + "_{0}".format(index),
self.get_bl_name() + "_{0}".format(index),
self.get_br_name() + "_{0}".format(index),
self.en_name + "_{0}".format(0), "vdd", "gnd"])
else:
self.connect_inst([self.data_name + "_{0}".format(index),
self.get_bl_name() + "_{0}".format(index),
self.get_br_name() + "_{0}".format(index),
self.en_name, "vdd", "gnd"])
for i in range(self.num_spare_cols):
index = self.word_size + i
if self.write_size:
offset = self.num_wmasks
else:
offset = 1
name = "write_driver{}".format(self.columns + i)
self.driver_insts[index]=self.add_inst(name=name,
mod=self.driver)
self.connect_inst([self.data_name + "_{0}".format(index),
self.get_bl_name() + "_{0}".format(index),
self.get_br_name() + "_{0}".format(index),
self.en_name + "_{0}".format(i + offset), "vdd", "gnd"])
def place_write_array(self):
from tech import cell_properties
if self.bitcell.width > self.driver.width:
self.driver_spacing = self.bitcell.width
else:
self.driver_spacing = self.driver.width
for i in range(0, self.columns, self.words_per_row):
index = int(i / self.words_per_row)
xoffset = i * self.driver_spacing
if cell_properties.bitcell.mirror.y and (i + self.column_offset) % 2:
mirror = "MY"
xoffset = xoffset + self.driver.width
else:
mirror = ""
base = vector(xoffset, 0)
self.driver_insts[index].place(offset=base, mirror=mirror)
# place spare write drivers (if spare columns are specified)
for i in range(self.num_spare_cols):
index = self.word_size + i
xoffset = (self.columns + i) * self.driver_spacing
if cell_properties.bitcell.mirror.y and (i + self.column_offset) % 2:
mirror = "MY"
xoffset = xoffset + self.driver.width
else:
mirror = ""
base = vector(xoffset, 0)
self.driver_insts[index].place(offset=base, mirror=mirror)
def add_layout_pins(self):
for i in range(self.word_size + self.num_spare_cols):
inst = self.driver_insts[i]
din_pin = inst.get_pin(inst.mod.din_name)
self.add_layout_pin(text=self.data_name + "_{0}".format(i),
layer=din_pin.layer,
offset=din_pin.ll(),
width=din_pin.width(),
height=din_pin.height())
bl_pin = inst.get_pin(inst.mod.get_bl_names())
self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i),
layer=bl_pin.layer,
offset=bl_pin.ll(),
width=bl_pin.width(),
height=bl_pin.height())
br_pin = inst.get_pin(inst.mod.get_br_names())
self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i),
layer=br_pin.layer,
offset=br_pin.ll(),
width=br_pin.width(),
height=br_pin.height())
for n in ["vdd", "gnd"]:
pin_list = self.driver_insts[i].get_pins(n)
for pin in pin_list:
self.add_power_pin(name=n,
loc=pin.center(),
directions=("V", "V"),
start_layer=pin.layer)
if self.write_size:
for bit in range(self.num_wmasks):
inst = self.driver_insts[bit * self.write_size]
en_pin = inst.get_pin(inst.mod.en_name)
# Determine width of wmask modified en_pin with/without col mux
wmask_en_len = self.words_per_row * (self.write_size * self.driver_spacing)
if (self.words_per_row == 1):
en_gap = self.driver_spacing - en_pin.width()
else:
en_gap = self.driver_spacing
self.add_layout_pin(text=self.en_name + "_{0}".format(bit),
layer=en_pin.layer,
offset=en_pin.ll(),
width=wmask_en_len - en_gap,
height=en_pin.height())
for i in range(self.num_spare_cols):
inst = self.driver_insts[self.word_size + i]
en_pin = inst.get_pin(inst.mod.en_name)
self.add_layout_pin(text=self.en_name + "_{0}".format(i + self.num_wmasks),
layer="m1",
offset=en_pin.lr() + vector(-drc("minwidth_m1"),0))
elif self.num_spare_cols and not self.write_size:
# shorten enable rail to accomodate those for spare write drivers
inst = self.driver_insts[0]
en_pin = inst.get_pin(inst.mod.en_name)
self.add_layout_pin(text=self.en_name + "_{0}".format(0),
layer="m1",
offset=en_pin.ll(),
width=self.width_regular_cols - self.words_per_row * en_pin.width())
# individual enables for every spare write driver
for i in range(self.num_spare_cols):
inst = self.driver_insts[self.word_size + i]
en_pin = inst.get_pin(inst.mod.en_name)
self.add_layout_pin(text=self.en_name + "_{0}".format(i + 1),
layer="m1",
offset=en_pin.lr() + vector(-drc("minwidth_m1"),0))
else:
inst = self.driver_insts[0]
self.add_layout_pin(text=self.en_name,
layer="m1",
offset=inst.get_pin(inst.mod.en_name).ll().scale(0, 1),
width=self.width)
def get_w_en_cin(self):
"""Get the relative capacitance of all the enable connections in the bank"""
# The enable is connected to a nand2 for every row.
return self.driver.get_w_en_cin() * len(self.driver_insts)

3
compiler/modules/dff_buf.py
View File

@ -7,7 +7,7 @@
# #
import debug import debug
import design import design
from tech import parameter, layer from tech import layer
from tech import cell_properties as props from tech import cell_properties as props
from vector import vector from vector import vector
from globals import OPTS from globals import OPTS
@ -23,7 +23,6 @@ class dff_buf(design.design):
unique_id = 1 unique_id = 1
def __init__(self, inv1_size=2, inv2_size=4, name=""): def __init__(self, inv1_size=2, inv2_size=4, name=""):
if name=="": if name=="":
name = "dff_buf_{0}".format(dff_buf.unique_id) name = "dff_buf_{0}".format(dff_buf.unique_id)
dff_buf.unique_id += 1 dff_buf.unique_id += 1

4
compiler/modules/replica_column.py
View File

@ -77,9 +77,9 @@ class replica_column(bitcell_base_array):
self.add_pin("gnd", "GROUND") self.add_pin("gnd", "GROUND")
def add_modules(self): def add_modules(self):
self.replica_cell = factory.create(module_type="replica_{}".format(OPTS.bitcell)) self.replica_cell = factory.create(module_type=OPTS.replica_bitcell)
self.add_mod(self.replica_cell) self.add_mod(self.replica_cell)
self.dummy_cell = factory.create(module_type="dummy_{}".format(OPTS.bitcell)) self.dummy_cell = factory.create(module_type=OPTS.dummy_bitcell)
self.add_mod(self.dummy_cell) self.add_mod(self.dummy_cell)
try: try:
edge_module_type = ("col_cap" if cell_properties.bitcell.end_caps else "dummy") edge_module_type = ("col_cap" if cell_properties.bitcell.end_caps else "dummy")

1
compiler/pgates/pand2.py
View File

@ -146,4 +146,3 @@ class pand2(pgate.pgate):
offset=pin.center(), offset=pin.center(),
width=pin.width(), width=pin.width(),
height=pin.height()) height=pin.height())

1
compiler/pgates/pand3.py
View File

@ -161,4 +161,3 @@ class pand3(pgate.pgate):
slew=nand_delay.slew, slew=nand_delay.slew,
load=load) load=load)
return nand_delay + inv_delay return nand_delay + inv_delay

1
compiler/pgates/pdriver.py
View File

@ -168,4 +168,3 @@ class pdriver(pgate.pgate):
def get_sizes(self): def get_sizes(self):
""" Return the relative sizes of the buffers """ """ Return the relative sizes of the buffers """
return self.size_list return self.size_list

2
compiler/sram/sram_config.py
View File

@ -39,7 +39,7 @@ class sram_config:
def compute_sizes(self): def compute_sizes(self):
""" Computes the organization of the memory using bitcell size by trying to make it square.""" """ Computes the organization of the memory using bitcell size by trying to make it square."""
bitcell = factory.create(module_type="bitcell") bitcell = factory.create(module_type=OPTS.bitcell, cell_name=OPTS.bitcell_name)
debug.check(self.num_banks in [1, 2, 4], debug.check(self.num_banks in [1, 2, 4],
"Valid number of banks are 1 , 2 and 4.") "Valid number of banks are 1 , 2 and 4.")

2
compiler/sram_factory.py
View File

@ -125,7 +125,7 @@ class sram_factory:
module_name = real_module_type module_name = real_module_type
else: else:
if self.is_duplicate_name(module_name): if self.is_duplicate_name(module_name):
raise ValueError("Modules with duplicate name are not allowed." \ raise ValueError("Modules with duplicate name are not allowed."
" '{}'".format(module_name)) " '{}'".format(module_name))
# type_str = "type={}".format(real_module_type) # type_str = "type={}".format(real_module_type)

4
compiler/tests/04_dff_buf_test.py
View File

@ -8,19 +8,19 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
class dff_buf_test(openram_test): class dff_buf_test(openram_test):
def runTest(self): def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file) globals.init_openram(config_file)
debug.info(2, "Testing dff_buf 4x 8x") debug.info(2, "Testing dff_buf 4x 8x")
a = factory.create(module_type="dff_buf", inv1_size=4, inv2_size=8) a = factory.create(module_type="dff_buf", inv1_size=4, inv2_size=8)
self.local_check(a) self.local_check(a)

3
compiler/tests/06_hierarchical_decoder_test.py
View File

@ -22,11 +22,10 @@ class hierarchical_decoder_test(openram_test):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file) globals.init_openram(config_file)
# Use the 2 port cell since it is usually bigger/easier
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.num_rw_ports = 1 OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1 OPTS.num_r_ports = 1
OPTS.num_w_ports = 0 OPTS.num_w_ports = 0
globals.setup_bitcell()
# Checks 2x4 and 2-input NAND decoder # Checks 2x4 and 2-input NAND decoder
debug.info(1, "Testing 16 row sample for hierarchical_decoder") debug.info(1, "Testing 16 row sample for hierarchical_decoder")

2
compiler/tests/06_hierarchical_predecode4x16_test.py
View File

@ -24,10 +24,10 @@ class hierarchical_predecode4x16_test(openram_test):
globals.init_openram(config_file) globals.init_openram(config_file)
# Use the 2 port cell since it is usually bigger/easier # Use the 2 port cell since it is usually bigger/easier
OPTS.bitcell = "bitcell_1rw_1r"
OPTS.num_rw_ports = 1 OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1 OPTS.num_r_ports = 1
OPTS.num_w_ports = 0 OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(1, "Testing sample for hierarchy_predecode4x16") debug.info(1, "Testing sample for hierarchy_predecode4x16")
a = factory.create(module_type="hierarchical_predecode4x16") a = factory.create(module_type="hierarchical_predecode4x16")

11
compiler/tests/14_replica_column_test.py
View File

@ -6,28 +6,31 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
class replica_column_test(openram_test): class replica_column_test(openram_test):
def runTest(self): def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME")) config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file) globals.init_openram(config_file)
debug.info(2, "Testing replica column for 6t_cell") debug.info(2, "Testing replica column for cell_6t")
a = factory.create(module_type="replica_column", rows=4, rbl=[1, 0], replica_bit=1) a = factory.create(module_type="replica_column", rows=4, rbl=[1, 0], replica_bit=1)
self.local_check(a) self.local_check(a)
debug.info(2, "Testing replica column for 6t_cell") debug.info(2, "Testing replica column for cell_1rw_1r")
globals.setup_bitcell()
a = factory.create(module_type="replica_column", rows=4, rbl=[1, 1], replica_bit=6) a = factory.create(module_type="replica_column", rows=4, rbl=[1, 1], replica_bit=6)
self.local_check(a) self.local_check(a)
debug.info(2, "Testing replica column for 6t_cell") debug.info(2, "Testing replica column for cell_1rw_1r")
globals.setup_bitcell()
a = factory.create(module_type="replica_column", rows=4, rbl=[2, 0], replica_bit=2) a = factory.create(module_type="replica_column", rows=4, rbl=[2, 0], replica_bit=2)
self.local_check(a) self.local_check(a)

5
compiler/tests/18_port_data_spare_cols_test.py
View File

@ -6,13 +6,14 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
class port_data_spare_cols_test(openram_test): class port_data_spare_cols_test(openram_test):
def runTest(self): def runTest(self):
@ -58,10 +59,10 @@ class port_data_spare_cols_test(openram_test):
a = factory.create("port_data", sram_config=c, port=0) a = factory.create("port_data", sram_config=c, port=0)
self.local_check(a) self.local_check(a)
OPTS.bitcell = "bitcell_1w_1r"
OPTS.num_rw_ports = 0 OPTS.num_rw_ports = 0
OPTS.num_r_ports = 1 OPTS.num_r_ports = 1
OPTS.num_w_ports = 1 OPTS.num_w_ports = 1
globals.setup_bitcell()
c.num_words=16 c.num_words=16
c.words_per_row=1 c.words_per_row=1

2
compiler/tests/18_port_data_wmask_1rw_1r_test.py
View File

@ -62,10 +62,10 @@ class port_data_wmask_1rw_1r_test(openram_test):
a = factory.create("port_data", sram_config=c, port=0) a = factory.create("port_data", sram_config=c, port=0)
self.local_check(a) self.local_check(a)
OPTS.bitcell = "bitcell_1w_1r"
OPTS.num_rw_ports = 0 OPTS.num_rw_ports = 0
OPTS.num_r_ports = 1 OPTS.num_r_ports = 1
OPTS.num_w_ports = 1 OPTS.num_w_ports = 1
globals.setup_bitcell()
c.num_words = 16 c.num_words = 16
c.words_per_row = 1 c.words_per_row = 1

2
compiler/tests/18_port_data_wmask_test.py
View File

@ -57,10 +57,10 @@ class port_data_wmask_test(openram_test):
a = factory.create("port_data", sram_config=c, port=0) a = factory.create("port_data", sram_config=c, port=0)
self.local_check(a) self.local_check(a)
OPTS.bitcell = "bitcell_1w_1r"
OPTS.num_rw_ports = 0 OPTS.num_rw_ports = 0
OPTS.num_r_ports = 1 OPTS.num_r_ports = 1
OPTS.num_w_ports = 1 OPTS.num_w_ports = 1
globals.setup_bitcell()
c.num_words = 16 c.num_words = 16
c.words_per_row = 1 c.words_per_row = 1

5
compiler/tests/19_psingle_bank_test.py
View File

@ -8,14 +8,14 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
#@unittest.skip("SKIPPING 19_psingle_bank_test")
class psingle_bank_test(openram_test): class psingle_bank_test(openram_test):
def runTest(self): def runTest(self):
@ -30,6 +30,7 @@ class psingle_bank_test(openram_test):
OPTS.num_rw_ports = 1 OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0 OPTS.num_w_ports = 0
OPTS.num_r_ports = 0 OPTS.num_r_ports = 0
globals.setup_bitcell()
c = sram_config(word_size=4, c = sram_config(word_size=4,
num_words=16) num_words=16)

3
compiler/tests/19_single_bank_1w_1r_test.py
View File

@ -8,13 +8,14 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
class single_bank_1w_1r_test(openram_test): class single_bank_1w_1r_test(openram_test):
def runTest(self): def runTest(self):

3
compiler/tests/19_single_bank_test.py
View File

@ -8,13 +8,14 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
class single_bank_test(openram_test): class single_bank_test(openram_test):
def runTest(self): def runTest(self):

4
compiler/tests/20_psram_1bank_2mux_1rw_1w_test.py
View File

@ -8,14 +8,14 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
#@unittest.skip("SKIPPING 20_psram_1bank_test, multiport layout not complete")
class psram_1bank_2mux_1rw_1w_test(openram_test): class psram_1bank_2mux_1rw_1w_test(openram_test):
def runTest(self): def runTest(self):

4
compiler/tests/20_psram_1bank_2mux_1rw_1w_wmask_test.py
View File

@ -9,7 +9,6 @@
import unittest import unittest
from testutils import * from testutils import *
import sys, os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
@ -26,11 +25,10 @@ class psram_1bank_2mux_1rw_1w_wmask_test(openram_test):
from sram_config import sram_config from sram_config import sram_config
OPTS.bitcell = "pbitcell" OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell = "replica_pbitcell"
OPTS.dummy_bitcell = "dummy_pbitcell"
OPTS.num_rw_ports = 1 OPTS.num_rw_ports = 1
OPTS.num_w_ports = 1 OPTS.num_w_ports = 1
OPTS.num_r_ports = 0 OPTS.num_r_ports = 0
globals.setup_bitcell()
c = sram_config(word_size=8, c = sram_config(word_size=8,
write_size=4, write_size=4,

4
compiler/tests/20_psram_1bank_2mux_1w_1r_test.py
View File

@ -8,14 +8,14 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
#@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error")
class psram_1bank_2mux_1w_1r_test(openram_test): class psram_1bank_2mux_1w_1r_test(openram_test):
def runTest(self): def runTest(self):

4
compiler/tests/20_psram_1bank_2mux_test.py
View File

@ -8,14 +8,14 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
#@unittest.skip("SKIPPING 20_psram_1bank_2mux_test, wide metal supply routing error")
class psram_1bank_2mux_test(openram_test): class psram_1bank_2mux_test(openram_test):
def runTest(self): def runTest(self):

3
compiler/tests/20_psram_1bank_4mux_1rw_1r_test.py
View File

@ -8,13 +8,14 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
class psram_1bank_4mux_1rw_1r_test(openram_test): class psram_1bank_4mux_1rw_1r_test(openram_test):
def runTest(self): def runTest(self):

3
compiler/tests/20_sram_1bank_2mux_1rw_1r_spare_cols_test.py
View File

@ -8,13 +8,14 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
class sram_1bank_2mux_1rw_1r_spare_cols_test(openram_test): class sram_1bank_2mux_1rw_1r_spare_cols_test(openram_test):
def runTest(self): def runTest(self):

3
compiler/tests/20_sram_1bank_2mux_1rw_1r_test.py
View File

@ -8,13 +8,14 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
class sram_1bank_2mux_1rw_1r_test(openram_test): class sram_1bank_2mux_1rw_1r_test(openram_test):
def runTest(self): def runTest(self):

4
compiler/tests/20_sram_1bank_2mux_1w_1r_spare_cols_test.py
View File

@ -8,14 +8,14 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
#@unittest.skip("SKIPPING 20_sram_1bank_2mux_1w_1r_spare_cols_test, odd supply routing error")
class sram_1bank_2mux_1w_1r_spare_cols_test(openram_test): class sram_1bank_2mux_1w_1r_spare_cols_test(openram_test):
def runTest(self): def runTest(self):

4
compiler/tests/20_sram_1bank_2mux_1w_1r_test.py
View File

@ -8,14 +8,14 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
#@unittest.skip("SKIPPING 20_psram_1bank_2mux_1w_1r_test, odd supply routing error")
class psram_1bank_2mux_1w_1r_test(openram_test): class psram_1bank_2mux_1w_1r_test(openram_test):
def runTest(self): def runTest(self):

1
compiler/tests/20_sram_1bank_2mux_global_test.py
View File

@ -16,7 +16,6 @@ from sram_factory import factory
import debug import debug
#@unittest.skip("SKIPPING 20_sram_1bank_4mux_test")
class sram_1bank_2mux_global_test(openram_test): class sram_1bank_2mux_global_test(openram_test):
def runTest(self): def runTest(self):

4
compiler/tests/20_sram_1bank_2mux_test.py
View File

@ -8,14 +8,14 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
#@unittest.skip("SKIPPING 20_sram_1bank_2mux_test")
class sram_1bank_2mux_test(openram_test): class sram_1bank_2mux_test(openram_test):
def runTest(self): def runTest(self):

3
compiler/tests/20_sram_1bank_2mux_wmask_spare_cols_test.py
View File

@ -9,14 +9,13 @@
import unittest import unittest
from testutils import * from testutils import *
import sys, os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
# @unittest.skip("SKIPPING 20_sram_1bank_2mux_wmask_spare_cols_test")
class sram_1bank_2mux_wmask_spare_cols_test(openram_test): class sram_1bank_2mux_wmask_spare_cols_test(openram_test):
def runTest(self): def runTest(self):

2
compiler/tests/20_sram_1bank_2mux_wmask_test.py
View File

@ -9,7 +9,6 @@
import unittest import unittest
from testutils import * from testutils import *
import sys, os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
@ -17,7 +16,6 @@ from sram_factory import factory
import debug import debug
# @unittest.skip("SKIPPING 20_sram_1bank_2mux_wmask_test")
class sram_1bank_2mux_wmask_test(openram_test): class sram_1bank_2mux_wmask_test(openram_test):
def runTest(self): def runTest(self):

1
compiler/tests/20_sram_1bank_32b_1024_wmask_test.py
View File

@ -9,7 +9,6 @@
import unittest import unittest
from testutils import * from testutils import *
import sys, os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS

4
compiler/tests/20_sram_1bank_4mux_test.py
View File

@ -8,14 +8,14 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
#@unittest.skip("SKIPPING 20_sram_1bank_4mux_test")
class sram_1bank_4mux_test(openram_test): class sram_1bank_4mux_test(openram_test):
def runTest(self): def runTest(self):

3
compiler/tests/20_sram_1bank_8mux_1rw_1r_test.py
View File

@ -8,13 +8,14 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
class sram_1bank_8mux_1rw_1r_test(openram_test): class sram_1bank_8mux_1rw_1r_test(openram_test):
def runTest(self): def runTest(self):

4
compiler/tests/20_sram_1bank_8mux_test.py
View File

@ -8,14 +8,14 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
#@unittest.skip("SKIPPING 20_sram_1bank_8mux_test")
class sram_1bank_8mux_test(openram_test): class sram_1bank_8mux_test(openram_test):
def runTest(self): def runTest(self):

3
compiler/tests/20_sram_1bank_nomux_1rw_1r_spare_cols_test.py
View File

@ -8,13 +8,14 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
class sram_1bank_nomux_1rw_1r_spare_cols_test(openram_test): class sram_1bank_nomux_1rw_1r_spare_cols_test(openram_test):
def runTest(self): def runTest(self):

3
compiler/tests/20_sram_1bank_nomux_1rw_1r_test.py
View File

@ -8,13 +8,14 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
class sram_1bank_nomux_1rw_1r_test(openram_test): class sram_1bank_nomux_1rw_1r_test(openram_test):
def runTest(self): def runTest(self):

2
compiler/tests/20_sram_1bank_nomux_spare_cols_test.py
View File

@ -9,7 +9,6 @@
import unittest import unittest
from testutils import * from testutils import *
import sys, os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
@ -17,7 +16,6 @@ from sram_factory import factory
import debug import debug
# @unittest.skip("SKIPPING 20_sram_1bank_nomux_spare_cols_test")
class sram_1bank_nomux_spare_cols_test(openram_test): class sram_1bank_nomux_spare_cols_test(openram_test):
def runTest(self): def runTest(self):

4
compiler/tests/20_sram_1bank_nomux_test.py
View File

@ -8,14 +8,14 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
#@unittest.skip("SKIPPING 20_sram_1bank_nomux_test")
class sram_1bank_nomux_test(openram_test): class sram_1bank_nomux_test(openram_test):
def runTest(self): def runTest(self):

1
compiler/tests/20_sram_1bank_nomux_wmask_sparecols_test.py
View File

@ -9,7 +9,6 @@
import unittest import unittest
from testutils import * from testutils import *
import sys, os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS

2
compiler/tests/20_sram_1bank_nomux_wmask_test.py
View File

@ -9,7 +9,6 @@
import unittest import unittest
from testutils import * from testutils import *
import sys, os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
@ -17,7 +16,6 @@ from sram_factory import factory
import debug import debug
# @unittest.skip("SKIPPING 20_sram_1bank_nomux_wmask_test")
class sram_1bank_nomux_wmask_test(openram_test): class sram_1bank_nomux_wmask_test(openram_test):
def runTest(self): def runTest(self):

3
compiler/tests/20_sram_2bank_test.py
View File

@ -8,13 +8,14 @@
# #
import unittest import unittest
from testutils import * from testutils import *
import sys,os import sys, os
sys.path.append(os.getenv("OPENRAM_HOME")) sys.path.append(os.getenv("OPENRAM_HOME"))
import globals import globals
from globals import OPTS from globals import OPTS
from sram_factory import factory from sram_factory import factory
import debug import debug
@unittest.skip("Multibank is not working yet.") @unittest.skip("Multibank is not working yet.")
class sram_2bank_test(openram_test): class sram_2bank_test(openram_test):

4
technology/scn4m_subm/tech/setup.tcl
View File

@ -9,9 +9,13 @@ flatten class {-circuit1 dummy_cell_1w_1r}
flatten class {-circuit1 dummy_pbitcell} flatten class {-circuit1 dummy_pbitcell}
flatten class {-circuit1 dummy_pbitcell_0} flatten class {-circuit1 dummy_pbitcell_0}
flatten class {-circuit1 dummy_pbitcell_1} flatten class {-circuit1 dummy_pbitcell_1}
flatten class {-circuit1 dummy_pbitcell_2}
flatten class {-circuit1 dummy_pbitcell_3}
flatten class {-circuit1 pbitcell} flatten class {-circuit1 pbitcell}
flatten class {-circuit1 pbitcell_0} flatten class {-circuit1 pbitcell_0}
flatten class {-circuit1 pbitcell_1} flatten class {-circuit1 pbitcell_1}
flatten class {-circuit1 pbitcell_2}
flatten class {-circuit1 pbitcell_3}
property {-circuit1 nfet} remove as ad ps pd property {-circuit1 nfet} remove as ad ps pd
property {-circuit1 pfet} remove as ad ps pd property {-circuit1 pfet} remove as ad ps pd
property {-circuit2 n} remove as ad ps pd property {-circuit2 n} remove as ad ps pd