Removed import cell since cell is removed from simplified txt file

compiler/TODO

@@ -28,3 +28,5 @@ hierarchical_predecode3x8 to hierarchical_predecode class
 
 Fix stimuli.py to be more readable.
 
+Change the delay measurement to be from the negative clock edge to 
+remove the dependency on the clock period.

compiler/bank.py

@@ -1,5 +1,5 @@
 import sys
-from tech import drc, parameter, cell
+from tech import drc, parameter
 import debug
 import design
 import math

compiler/control_logic.py

@@ -1,6 +1,6 @@
 from math import log
 import design
-from tech import drc, parameter, cell
+from tech import drc, parameter
 import debug
 from ms_flop_array import ms_flop_array
 from wordline_driver import wordline_driver

compiler/hierarchical_decoder.py

@@ -1,4 +1,4 @@
-from tech import drc, cell
+from tech import drc
 import debug
 import design
 from math import log

compiler/hierarchical_predecode.py

@@ -1,7 +1,7 @@
 import debug
 import design
 import math
-from tech import drc, cell
+from tech import drc
 from contact import contact
 from nand_2 import nand_2
 from nand_3 import nand_3

compiler/logic_effort_dc.py

@@ -1,6 +1,6 @@
 import debug
 import design
-from tech import drc, cell
+from tech import drc
 from pinv import pinv
 from contact import contact
 from vector import vector

compiler/nand_2.py

@@ -1,7 +1,7 @@
 import contact
 import design
 import debug
-from tech import drc, cell
+from tech import drc
 from ptx import ptx
 from vector import vector
 from globals import OPTS

compiler/nand_3.py

@@ -1,7 +1,7 @@
 import contact
 import design
 import debug
-from tech import drc, cell
+from tech import drc
 from ptx import ptx
 from vector import vector
 from globals import OPTS

compiler/nor_2.py

@@ -1,7 +1,7 @@
 import contact
 import design
 import debug
-from tech import drc, cell
+from tech import drc
 from ptx import ptx
 from vector import vector
 from globals import OPTS

compiler/pinv.py

@@ -1,7 +1,7 @@
 import contact
 import design
 import debug
-from tech import drc, parameter, cell
+from tech import drc, parameter
 from ptx import ptx
 from vector import vector
 from math import ceil

compiler/precharge.py

@@ -1,7 +1,7 @@
 from contact import contact
 import design
 import debug
-from tech import drc, cell
+from tech import drc
 from ptx import ptx
 from vector import vector
 from globals import OPTS

compiler/replica_bitline.py

@@ -1,6 +1,6 @@
 import debug
 import design
-from tech import drc, cell
+from tech import drc
 from pinv import pinv
 from contact import contact
 from bitcell_array import bitcell_array

compiler/single_level_column_mux.py

@@ -1,6 +1,6 @@
 import design
 import debug
-from tech import drc, cell
+from tech import drc
 from vector import vector
 from contact import contact
 from ptx import ptx

compiler/sram.py

@@ -1,6 +1,6 @@
 import math
 import sys
-from tech import drc, spice, cell
+from tech import drc, spice
 import debug
 import design
 from math import log,sqrt,ceil

compiler/wordline_driver.py

@@ -1,4 +1,4 @@
-from tech import drc, parameter, cell
+from tech import drc, parameter
 import debug
 import design
 from math import log