diff --git a/compiler/TODO b/compiler/TODO
index 31cde6d5..e8750fbc 100644
--- a/compiler/TODO
+++ b/compiler/TODO
@@ -28,3 +28,5 @@ hierarchical_predecode3x8 to hierarchical_predecode class
 
 Fix stimuli.py to be more readable.
 
+Change the delay measurement to be from the negative clock edge to 
+remove the dependency on the clock period.
\ No newline at end of file
diff --git a/compiler/bank.py b/compiler/bank.py
index df146da9..7cb2ba12 100644
--- a/compiler/bank.py
+++ b/compiler/bank.py
@@ -1,5 +1,5 @@
 import sys
-from tech import drc, parameter, cell
+from tech import drc, parameter
 import debug
 import design
 import math
diff --git a/compiler/control_logic.py b/compiler/control_logic.py
index 3cda5e85..e08663ad 100644
--- a/compiler/control_logic.py
+++ b/compiler/control_logic.py
@@ -1,6 +1,6 @@
 from math import log
 import design
-from tech import drc, parameter, cell
+from tech import drc, parameter
 import debug
 from ms_flop_array import ms_flop_array
 from wordline_driver import wordline_driver
diff --git a/compiler/hierarchical_decoder.py b/compiler/hierarchical_decoder.py
index 5b4c590f..e964cc2a 100644
--- a/compiler/hierarchical_decoder.py
+++ b/compiler/hierarchical_decoder.py
@@ -1,4 +1,4 @@
-from tech import drc, cell
+from tech import drc
 import debug
 import design
 from math import log
diff --git a/compiler/hierarchical_predecode.py b/compiler/hierarchical_predecode.py
index 65a7fd2d..0b2566f8 100644
--- a/compiler/hierarchical_predecode.py
+++ b/compiler/hierarchical_predecode.py
@@ -1,7 +1,7 @@
 import debug
 import design
 import math
-from tech import drc, cell
+from tech import drc
 from contact import contact
 from nand_2 import nand_2
 from nand_3 import nand_3
diff --git a/compiler/logic_effort_dc.py b/compiler/logic_effort_dc.py
index 115ff8a7..df7f178f 100644
--- a/compiler/logic_effort_dc.py
+++ b/compiler/logic_effort_dc.py
@@ -1,6 +1,6 @@
 import debug
 import design
-from tech import drc, cell
+from tech import drc
 from pinv import pinv
 from contact import contact
 from vector import vector
diff --git a/compiler/nand_2.py b/compiler/nand_2.py
index 1780c552..4b97aa61 100644
--- a/compiler/nand_2.py
+++ b/compiler/nand_2.py
@@ -1,7 +1,7 @@
 import contact
 import design
 import debug
-from tech import drc, cell
+from tech import drc
 from ptx import ptx
 from vector import vector
 from globals import OPTS
diff --git a/compiler/nand_3.py b/compiler/nand_3.py
index ede069c9..7e4904e1 100644
--- a/compiler/nand_3.py
+++ b/compiler/nand_3.py
@@ -1,7 +1,7 @@
 import contact
 import design
 import debug
-from tech import drc, cell
+from tech import drc
 from ptx import ptx
 from vector import vector
 from globals import OPTS
diff --git a/compiler/nor_2.py b/compiler/nor_2.py
index 9138c8eb..8e22f30c 100644
--- a/compiler/nor_2.py
+++ b/compiler/nor_2.py
@@ -1,7 +1,7 @@
 import contact
 import design
 import debug
-from tech import drc, cell
+from tech import drc
 from ptx import ptx
 from vector import vector
 from globals import OPTS
diff --git a/compiler/pinv.py b/compiler/pinv.py
index 935304bd..3bad3d81 100644
--- a/compiler/pinv.py
+++ b/compiler/pinv.py
@@ -1,7 +1,7 @@
 import contact
 import design
 import debug
-from tech import drc, parameter, cell
+from tech import drc, parameter
 from ptx import ptx
 from vector import vector
 from math import ceil
diff --git a/compiler/precharge.py b/compiler/precharge.py
index 4241abc5..138df604 100644
--- a/compiler/precharge.py
+++ b/compiler/precharge.py
@@ -1,7 +1,7 @@
 from contact import contact
 import design
 import debug
-from tech import drc, cell
+from tech import drc
 from ptx import ptx
 from vector import vector
 from globals import OPTS
diff --git a/compiler/replica_bitline.py b/compiler/replica_bitline.py
index 9e3e70b9..cd91b4bf 100644
--- a/compiler/replica_bitline.py
+++ b/compiler/replica_bitline.py
@@ -1,6 +1,6 @@
 import debug
 import design
-from tech import drc, cell
+from tech import drc
 from pinv import pinv
 from contact import contact
 from bitcell_array import bitcell_array
diff --git a/compiler/single_level_column_mux.py b/compiler/single_level_column_mux.py
index 005ce54c..30c32176 100644
--- a/compiler/single_level_column_mux.py
+++ b/compiler/single_level_column_mux.py
@@ -1,6 +1,6 @@
 import design
 import debug
-from tech import drc, cell
+from tech import drc
 from vector import vector
 from contact import contact
 from ptx import ptx
diff --git a/compiler/sram.py b/compiler/sram.py
index ffa70454..67a12817 100644
--- a/compiler/sram.py
+++ b/compiler/sram.py
@@ -1,6 +1,6 @@
 import math
 import sys
-from tech import drc, spice, cell
+from tech import drc, spice
 import debug
 import design
 from math import log,sqrt,ceil
diff --git a/compiler/wordline_driver.py b/compiler/wordline_driver.py
index d8fe27a9..5a7de1b7 100644
--- a/compiler/wordline_driver.py
+++ b/compiler/wordline_driver.py
@@ -1,4 +1,4 @@
-from tech import drc, parameter, cell
+from tech import drc, parameter
 import debug
 import design
 from math import log