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Use layer stacks from tech file in design class and throughout

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This commit is contained in:
Matt Guthaus
2019-12-13 14:13:41 -08:00
parent 8d3f1d19cb
commit e143a6033f
28 changed files with 141 additions and 132 deletions
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compiler/modules/bank.py
+7 -7
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@@ -606,11 +606,11 @@ class bank(design.design):
name = self.control_signals[port][signal]
bus_pos = vector(self.bus_xoffset[port][name].x, out_pos.y)
self.add_path("metal3",[out_pos, bus_pos])
self.add_via_center(layers=("metal2", "via2", "metal3"),
self.add_via_center(layers=self.m2_stack,
offset=bus_pos)
self.add_via_center(layers=("metal1", "via1", "metal2"),
self.add_via_center(layers=self.m1_stack,
offset=out_pos)
self.add_via_center(layers=("metal2", "via2", "metal3"),
self.add_via_center(layers=self.m2_stack,
offset=out_pos)
@@ -756,7 +756,7 @@ class bank(design.design):
bottom_names = [bottom_inst.get_pin(bottom_bl_name.format(bit)), bottom_inst.get_pin(bottom_br_name.format(bit))]
top_names = [top_inst.get_pin(top_bl_name.format(bit)), top_inst.get_pin(top_br_name.format(bit))]
route_map = list(zip(bottom_names, top_names))
self.create_horizontal_channel_route(route_map, offset)
self.create_horizontal_channel_route(route_map, offset, self.m1_stack)
def connect_bitline(self, inst1, inst2, inst1_name, inst2_name):
"""
@@ -865,7 +865,7 @@ class bank(design.design):
column_mux_pins = [self.port_data_inst[port].get_pin(x) for x in sel_names]
route_map = list(zip(decode_pins, column_mux_pins))
self.create_vertical_channel_route(route_map, offset)
self.create_vertical_channel_route(route_map, offset, self.m1_stack)
def add_lvs_correspondence_points(self):
@@ -942,7 +942,7 @@ class bank(design.design):
control_mid_pos = self.bus_xoffset[port][control_signal]
control_pos = vector(self.bus_xoffset[port][control_signal].x ,pin_pos.y)
self.add_wire(("metal1","via1","metal2"), [control_mid_pos, control_pos, pin_pos])
self.add_via_center(layers=("metal1", "via1", "metal2"),
self.add_via_center(layers=self.m1_stack,
offset=control_pos)
@@ -957,7 +957,7 @@ class bank(design.design):
control_x_offset = self.bus_xoffset[port][control_signal].x
control_pos = vector(control_x_offset, mid_pos.y)
self.add_wire(("metal1","via1","metal2"),[pin_pos, mid_pos, control_pos])
self.add_via_center(layers=("metal1", "via1", "metal2"),
self.add_via_center(layers=self.m1_stack,
offset=control_pos)
def determine_wordline_stage_efforts(self, external_cout, inp_is_rise=True):
compiler/modules/bank_select.py
+5 -5
View File
@@ -258,7 +258,7 @@ class bank_select(design.design):
logic_pos = logic_inst.get_pin("B").lc() - vector(0.5*contact.m1m2.height,0)
input_pos = vector(xoffset_bank_signal, logic_pos.y)
self.add_path("metal2",[logic_pos, input_pos])
self.add_via_center(layers=("metal1", "via1", "metal2"),
self.add_via_center(layers=self.m1_stack,
offset=logic_pos,
directions=("H","H"))
@@ -266,10 +266,10 @@ class bank_select(design.design):
# Connect the logic A input to the input pin
logic_pos = logic_inst.get_pin("A").lc()
input_pos = vector(0,logic_pos.y)
self.add_via_center(layers=("metal1", "via1", "metal2"),
self.add_via_center(layers=self.m1_stack,
offset=logic_pos,
directions=("H","H"))
self.add_via_center(layers=("metal2", "via2", "metal3"),
self.add_via_center(layers=self.m2_stack,
offset=logic_pos,
directions=("H","H"))
self.add_layout_pin_segment_center(text=input_name,
@@ -301,10 +301,10 @@ class bank_select(design.design):
# Add pins in two locations
for xoffset in [a_xoffset, b_xoffset]:
pin_pos = vector(xoffset, supply_pin.cy())
self.add_via_center(layers=("metal1", "via1", "metal2"),
self.add_via_center(layers=self.m1_stack,
offset=pin_pos,
directions=("H","H"))
self.add_via_center(layers=("metal2", "via2", "metal3"),
self.add_via_center(layers=self.m2_stack,
offset=pin_pos,
directions=("H","H"))
self.add_layout_pin_rect_center(text=n,
compiler/modules/hierarchical_decoder.py
+5 -5
View File
@@ -221,9 +221,9 @@ class hierarchical_decoder(design.design):
def route_input_rail(self, input_offset, output_offset):
""" Route a vertical M2 coordinate to another vertical M2 coordinate to the predecode inputs """
self.add_via_center(layers=("metal2", "via2", "metal3"),
self.add_via_center(layers=self.m2_stack,
offset=input_offset)
self.add_via_center(layers=("metal2", "via2", "metal3"),
self.add_via_center(layers=self.m2_stack,
offset=output_offset)
self.add_path(("metal3"), [input_offset, output_offset])
@@ -585,7 +585,7 @@ class hierarchical_decoder(design.design):
""" Connect the routing rail to the given metal1 pin """
rail_pos = vector(self.predecode_rails[rail_name].x,pin.lc().y)
self.add_path("metal1", [rail_pos, pin.lc()])
self.add_via_center(layers=("metal1", "via1", "metal2"),
self.add_via_center(layers=self.m1_stack,
offset=rail_pos)
@@ -595,10 +595,10 @@ class hierarchical_decoder(design.design):
# It would be fixed with a channel router.
mid_point = vector(pin.cx(), pin.cy()+self.inv.height/2)
rail_pos = vector(self.predecode_rails[rail_name].x,mid_point.y)
self.add_via_center(layers=("metal1", "via1", "metal2"),
self.add_via_center(layers=self.m1_stack,
offset=pin.center())
self.add_wire(("metal3","via2","metal2"), [rail_pos, mid_point, pin.uc()])
self.add_via_center(layers=("metal2", "via2", "metal3"),
self.add_via_center(layers=self.m2_stack,
offset=rail_pos)
def input_load(self):
compiler/modules/hierarchical_predecode.py
+5 -5
View File
@@ -184,9 +184,9 @@ class hierarchical_predecode(design.design):
in_pos = vector(self.input_rails[in_pin].x,y_offset)
a_pos = vector(self.decode_rails[a_pin].x,y_offset)
self.add_path("metal1",[in_pos, a_pos])
self.add_via_center(layers = ("metal1", "via1", "metal2"),
self.add_via_center(layers = self.m1_stack,
offset=[self.input_rails[in_pin].x, y_offset])
self.add_via_center(layers = ("metal1", "via1", "metal2"),
self.add_via_center(layers = self.m1_stack,
offset=[self.decode_rails[a_pin].x, y_offset])
def route_output_inverters(self):
@@ -227,7 +227,7 @@ class hierarchical_predecode(design.design):
right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").lx(),0)
rail_pos = vector(self.decode_rails[out_pin].x,y_offset)
self.add_path("metal1", [inv_out_pos, right_pos, vector(right_pos.x, y_offset), rail_pos])
self.add_via_center(layers = ("metal1", "via1", "metal2"),
self.add_via_center(layers = self.m1_stack,
offset=rail_pos)
@@ -235,7 +235,7 @@ class hierarchical_predecode(design.design):
inv_in_pos = self.in_inst[inv_num].get_pin("A").lc()
in_pos = vector(self.input_rails[in_pin].x,inv_in_pos.y)
self.add_path("metal1", [in_pos, inv_in_pos])
self.add_via_center(layers=("metal1", "via1", "metal2"),
self.add_via_center(layers=self.m1_stack,
offset=in_pos)
@@ -256,7 +256,7 @@ class hierarchical_predecode(design.design):
pin_pos = self.nand_inst[k].get_pin(gate_pin).lc()
rail_pos = vector(self.decode_rails[rail_pin].x, pin_pos.y)
self.add_path("metal1", [rail_pos, pin_pos])
self.add_via_center(layers=("metal1", "via1", "metal2"),
self.add_via_center(layers=self.m1_stack,
offset=rail_pos)
compiler/modules/multibank.py
+7 -7
View File
@@ -452,13 +452,13 @@ class multibank(design.design):
out_pos = self.bank_select_inst.get_pin(gated_name).rc()
bus_pos = vector(self.bus_xoffset[gated_name], out_pos.y)
self.add_path("metal3",[out_pos, bus_pos])
self.add_via_center(layers=("metal2", "via2", "metal3"),
self.add_via_center(layers=self.m2_stack,
offset=bus_pos,
rotate=90)
self.add_via_center(layers=("metal1", "via1", "metal2"),
self.add_via_center(layers=self.m1_stack,
offset=out_pos,
rotate=90)
self.add_via_center(layers=("metal2", "via2", "metal3"),
self.add_via_center(layers=self.m2_stack,
offset=out_pos,
rotate=90)
@@ -586,9 +586,9 @@ class multibank(design.design):
tri_gate_in = self.tri_gate_array_inst.get_pin("in_{}".format(i)).lc()
sa_data_out = self.sense_amp_array_inst.get_pin("data_{}".format(i)).bc()
self.add_via_center(layers=("metal2", "via2", "metal3"),
self.add_via_center(layers=self.m2_stack,
offset=tri_gate_in)
self.add_via_center(layers=("metal2", "via2", "metal3"),
self.add_via_center(layers=self.m2_stack,
offset=sa_data_out)
self.add_path("metal3",[sa_data_out,tri_gate_in])
@@ -766,7 +766,7 @@ class multibank(design.design):
for (control_signal, pin_pos) in connection:
control_pos = vector(self.bus_xoffset[control_signal].x ,pin_pos.y)
self.add_path("metal1", [control_pos, pin_pos])
self.add_via_center(layers=("metal1", "via1", "metal2"),
self.add_via_center(layers=self.m1_stack,
offset=control_pos,
rotate=90)
@@ -778,7 +778,7 @@ class multibank(design.design):
control_pos = vector(control_x_offset + self.m1_width, mid_pos.y)
self.add_wire(("metal1","via1","metal2"),[pin_pos, mid_pos, control_pos])
control_via_pos = vector(control_x_offset, mid_pos.y)
self.add_via_center(layers=("metal1", "via1", "metal2"),
self.add_via_center(layers=self.m1_stack,
offset=control_via_pos,
rotate=90)
compiler/modules/port_data.py
+2 -2
View File
@@ -475,7 +475,7 @@ class port_data(design.design):
end_pos = vector(length, wdriver_en_pin.cy())
# Add via for the write driver array's enable input
self.add_via_center(layers=("metal1", "via1", "metal2"),
self.add_via_center(layers=self.m1_stack,
offset=end_pos)
# Route between write mask AND array and write driver array
@@ -626,7 +626,7 @@ class port_data(design.design):
bottom_names = [bottom_inst.get_pin(bottom_bl_name.format(bit+bottom_start_bit)), bottom_inst.get_pin(bottom_br_name.format(bit+bottom_start_bit))]
top_names = [top_inst.get_pin(top_bl_name.format(bit+top_start_bit)), top_inst.get_pin(top_br_name.format(bit+top_start_bit))]
route_map = list(zip(bottom_names, top_names))
self.create_horizontal_channel_route(route_map, offset)
self.create_horizontal_channel_route(route_map, offset, self.m1_stack)
def connect_bitlines(self, inst1, inst2, num_bits,
compiler/modules/sense_amp_array.py
+2 -2
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@@ -99,13 +99,13 @@ class sense_amp_array(design.design):
inst = self.local_insts[i]
gnd_pos = inst.get_pin("gnd").center()
self.add_via_center(layers=("metal2", "via2", "metal3"),
self.add_via_center(layers=self.m2_stack,
offset=gnd_pos)
self.add_layout_pin_rect_center(text="gnd",
layer="metal3",
offset=gnd_pos)
vdd_pos = inst.get_pin("vdd").center()
self.add_via_center(layers=("metal2", "via2", "metal3"),
self.add_via_center(layers=self.m2_stack,
offset=vdd_pos)
self.add_layout_pin_rect_center(text="vdd",
layer="metal3",
compiler/modules/single_level_column_mux_array.py
+4 -4
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@@ -191,11 +191,11 @@ class single_level_column_mux_array(design.design):
# This via is on the right of the wire
self.add_via_center(layers=("metal1", "via1", "metal2"),
self.add_via_center(layers=self.m1_stack,
offset=bl_out_offset)
# This via is on the left of the wire
self.add_via_center(layers=("metal1", "via1", "metal2"),
self.add_via_center(layers=self.m1_stack,
offset=br_out_offset)
else:
@@ -204,10 +204,10 @@ class single_level_column_mux_array(design.design):
self.add_path("metal2", [ br_out_offset, br_out_offset_end])
# This via is on the right of the wire
self.add_via_center(layers=("metal1", "via1", "metal2"),
self.add_via_center(layers=self.m1_stack,
offset=bl_out_offset)
# This via is on the left of the wire
self.add_via_center(layers=("metal1", "via1", "metal2"),
self.add_via_center(layers=self.m1_stack,
offset=br_out_offset)
def get_drain_cin(self):
compiler/modules/tri_gate_array.py
+1 -1
View File
@@ -100,7 +100,7 @@ class tri_gate_array(design.design):
for n in ["vdd", "gnd"]:
for supply_pin in self.tri_inst[i].get_pins(n):
pin_pos = supply_pin.center()
self.add_via_center(layers=("metal2", "via2", "metal3"),
self.add_via_center(layers=self.m2_stack,
offset=pin_pos)
self.add_layout_pin_rect_center(text=n,
layer="metal3",
compiler/modules/wordline_driver.py
+3 -3
View File
@@ -158,7 +158,7 @@ class wordline_driver(design.design):
self.add_segment_center(layer="metal1",
start=clk_offset,
end=a_pos)
self.add_via_center(layers=("metal1", "via1", "metal2"),
self.add_via_center(layers=self.m1_stack,
offset=clk_offset)
# Nand2 out to 2nd inv
@@ -185,14 +185,14 @@ class wordline_driver(design.design):
layer="metal1",
start=input_offset,
end=mid_via_offset)
self.add_via_center(layers=("metal1", "via1", "metal2"),
self.add_via_center(layers=self.m1_stack,
offset=mid_via_offset,
directions=("V", "V"))
# now connect to the nand2 B
self.add_path("metal2", [mid_via_offset, b_pos])
contact_offset = b_pos - vector(0.5 * contact.m1m2.height, 0)
self.add_via_center(layers=("metal1", "via1", "metal2"),
self.add_via_center(layers=self.m1_stack,
offset=contact_offset,
directions=("H", "H"))
compiler/modules/write_driver_array.py
+1 -1
View File
@@ -143,7 +143,7 @@ class write_driver_array(design.design):
for pin in pin_list:
pin_pos = pin.center()
# Add the M2->M3 stack
self.add_via_center(layers=("metal2", "via2", "metal3"),
self.add_via_center(layers=self.m2_stack,
offset=pin_pos)
self.add_layout_pin_rect_center(text=n,
layer="metal3",
compiler/modules/write_mask_and_array.py
+4 -4
View File
@@ -117,9 +117,9 @@ class write_mask_and_array(design.design):
layer="metal3",
offset=beg_en_pin.bc(),
width=end_en_pin.cx() - beg_en_pin.cx() + en_to_edge)
self.add_via_center(layers=("metal1", "via1", "metal2"),
self.add_via_center(layers=self.m1_stack,
offset=vector(end_en_pin.cx() + en_to_edge, end_en_pin.cy()))
self.add_via_center(layers=("metal2", "via2", "metal3"),
self.add_via_center(layers=self.m2_stack,
offset=vector(end_en_pin.cx() + en_to_edge, end_en_pin.cy()))
else:
self.add_layout_pin(text="en",
@@ -134,9 +134,9 @@ class write_mask_and_array(design.design):
# Add via connections to metal3 for AND array's B pin
en_pin = self.and2_insts[i].get_pin("B")
self.add_via_center(layers=("metal1", "via1", "metal2"),
self.add_via_center(layers=self.m1_stack,
offset=en_pin.center())
self.add_via_center(layers=("metal2", "via2", "metal3"),
self.add_via_center(layers=self.m2_stack,
offset=en_pin.center())
self.add_power_pin("gnd", vector(supply_pin.width() + i * self.wmask_en_len, 0))