mirror of https://github.com/VLSIDA/OpenRAM.git
Fix missing rule
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76f7019432
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8d3f1d19cb
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@ -243,7 +243,7 @@ class pbitcell(bitcell_base.bitcell_base):
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(self.inverter_nmos.active_contact.height - self.inverter_nmos.active_height)
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self.inverter_gap = max(self.poly_to_active,
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self.m1_space + inverter_nmos_contact_extension) \
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+ self.poly_to_poly_contact + 2 * contact.poly.width \
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+ self.poly_to_contact + 2 * contact.poly.width \
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+ self.m1_space + inverter_pmos_contact_extension
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self.cross_couple_lower_ypos = self.inverter_nmos_ypos \
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+ self.inverter_nmos.active_height \
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@ -254,7 +254,7 @@ class pbitcell(bitcell_base.bitcell_base):
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+ self.inverter_nmos.active_height \
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+ max(self.poly_to_active,
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self.m1_space + inverter_nmos_contact_extension) \
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+ self.poly_to_poly_contact \
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+ self.poly_to_contact \
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+ 1.5 * contact.poly.width
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# spacing between wordlines (and gnd)
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@ -926,14 +926,14 @@ class pbitcell(bitcell_base.bitcell_base):
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"""
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# add poly to metal1 contacts for gates of the inverters
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left_storage_contact = vector(self.inverter_nmos_left.get_pin("G").lc().x \
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- self.poly_to_poly_contact - 0.5*contact.poly.width,
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- self.poly_to_contact - 0.5*contact.poly.width,
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self.cross_couple_upper_ypos)
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self.add_via_center(layers=("poly", "contact", "metal1"),
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offset=left_storage_contact,
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directions=("H", "H"))
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right_storage_contact = vector(self.inverter_nmos_right.get_pin("G").rc().x \
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+ self.poly_to_poly_contact + 0.5*contact.poly.width,
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+ self.poly_to_contact + 0.5*contact.poly.width,
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self.cross_couple_upper_ypos)
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self.add_via_center(layers=("poly", "contact", "metal1"),
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offset=right_storage_contact,
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