mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-02 02:57:53 +02:00
Begin adding wmask netlist and spice tests.
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jsowash
@@ -759,8 +759,6 @@ class control_logic(design.design):
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def route_dffs(self):
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if self.port_type == "rw":
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#print("hi")
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#if (self.word_size == self.write_size):
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dff_out_map = zip(["dout_bar_0", "dout_bar_1", "dout_1"], ["cs", "we", "we_bar"])
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elif self.port_type == "r":
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dff_out_map = zip(["dout_bar_0", "dout_0"], ["cs", "cs_bar"])
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@@ -187,9 +187,15 @@ class multibank(design.design):
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words_per_row=self.words_per_row)
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self.add_mod(self.sense_amp_array)
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self.write_driver_array = self.mod_write_driver_array(columns=self.num_cols,
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word_size=self.word_size)
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self.add_mod(self.write_driver_array)
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if (self.write_size != self.word_size):
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self.write_mask_driver_array = self.mod_write_mask_driver_array(columns=self.num_cols,
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word_size=self.word_size,
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write_size=self.write_size)
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self.add_mod(self.write_mask_driver_array)
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else:
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self.write_driver_array = self.mod_write_driver_array(columns=self.num_cols,
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word_size=self.word_size)
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self.add_mod(self.write_driver_array)
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self.row_decoder = self.mod_decoder(rows=self.num_rows)
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self.add_mod(self.row_decoder)
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@@ -21,6 +21,7 @@ class port_data(design.design):
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sram_config.set_local_config(self)
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self.port = port
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self.num_wmask = int(self.word_size/self.write_size)
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if name == "":
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name = "port_data_{0}".format(self.port)
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@@ -53,6 +54,8 @@ class port_data(design.design):
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if self.write_driver_array:
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self.create_write_driver_array()
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if (self.word_size != self.write_size):
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self.create_write_mask_array()
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else:
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self.write_driver_array_inst = None
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@@ -164,6 +167,12 @@ class port_data(design.design):
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columns=self.num_cols,
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word_size=self.word_size)
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self.add_mod(self.write_driver_array)
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if (self.word_size != self.write_size):
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self.write_mask_array = factory.create(module_type="write_mask_array",
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columns=self.num_cols,
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word_size=self.word_size,
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write_size=self.write_size)
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self.add_mod(self.write_driver_array)
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else:
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self.write_driver_array = None
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@@ -279,6 +288,18 @@ class port_data(design.design):
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temp.extend(["w_en", "vdd", "gnd"])
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self.connect_inst(temp)
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def create_write_mask_array(self):
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""" Creating Write Masks """
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self.write_mask_array_inst = self.add_inst(name="write_mask_array{}".format(self.port),
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mod=self.write_mask_array)
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temp = []
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for bit in range(self.num_wmask):
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temp.append("write_mask_".format(bit))
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temp.extend(["w_en", "vdd", "gnd"])
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self.connect_inst(temp)
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def place_write_driver_array(self, offset):
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""" Placing Write Driver """
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@@ -0,0 +1,158 @@
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from math import log
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import design
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from tech import drc
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import debug
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from sram_factory import factory
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from vector import vector
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from globals import OPTS
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class write_mask_array(design.design):
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"""
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Array of tristate drivers to write to the bitlines through the column mux.
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Dynamically generated write driver array of all bitlines.
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"""
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def __init__(self, name, columns, word_size, write_size):
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design.design.__init__(self, name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("columns: {0}".format(columns))
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self.add_comment("word_size {0}".format(word_size))
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self.add_comment("write_size {0}".format(write_size))
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self.columns = columns
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self.word_size = word_size
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self.write_size = write_size
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self.words_per_row = int(columns / word_size)
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self.num_wmask = int(word_size / write_size)
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self.create_netlist()
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# if not OPTS.netlist_only:
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# self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_write_mask_array()
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self.create_and2_array()
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# def create_layout(self):
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#
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# if self.bitcell.width > self.driver.width:
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# self.width = self.columns * self.bitcell.width
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# else:
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# self.width = self.columns * self.driver.width
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#
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# self.height = self.driver.height
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#
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# self.place_write_array()
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# self.add_layout_pins()
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# self.add_boundary()
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# self.DRC_LVS()
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def add_pins(self):
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for bit in range(self.num_wmask):
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self.add_pin("wdriver_sel_{}".format(bit))
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self.add_pin("en")
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self.add_pin("vdd")
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self.add_pin("gnd")
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def add_modules(self):
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self.wmask = factory.create(module_type="dff_buf")
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self.add_mod(self.wmask)
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dff_height = self.wmask.height
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self.and2 = factory.create(module_type="pand2",
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size=4,
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height=dff_height)
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self.add_mod(self.and2)
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def create_write_mask_array(self):
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self.wmask_insts = {}
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for bit in range(self.num_wmask):
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name = "write_mask_{}".format(bit)
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self.wmask_insts[bit] = self.add_inst(name=name,
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mod=self.wmask)
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self.connect_inst(["wmask_{}".format(bit),
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"bank_wmask_{}".format(bit),
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"bank_wmask_bar_{}".format(bit),
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"clk", "vdd", "gnd"])
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def create_and2_array(self):
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self.and2_insts = {}
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for bit in range(self.num_wmask):
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name = "and2_{}".format(bit)
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self.and2_insts[bit] = self.add_inst(name=name,
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mod=self.and2)
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self.connect_inst(["bank_wmask_{}".format(bit),
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"en",
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"wdriver_sel_{}".format(bit),
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"vdd", "gnd"])
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# def place_write_array(self):
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# if self.bitcell.width > self.driver.width:
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# driver_spacing = self.bitcell.width
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# else:
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# driver_spacing = self.driver.width
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#
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# for i in range(0, self.columns, self.words_per_row):
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# index = int(i / self.words_per_row)
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# base = vector(i * driver_spacing, 0)
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# self.driver_insts[index].place(base)
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# def add_layout_pins(self):
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# for i in range(self.word_size):
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# din_pin = self.driver_insts[i].get_pin("din")
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# self.add_layout_pin(text="data_{0}".format(i),
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# layer="metal2",
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# offset=din_pin.ll(),
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# width=din_pin.width(),
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# height=din_pin.height())
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# bl_pin = self.driver_insts[i].get_pin("bl")
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# self.add_layout_pin(text="bl_{0}".format(i),
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# layer="metal2",
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# offset=bl_pin.ll(),
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# width=bl_pin.width(),
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# height=bl_pin.height())
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#
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# br_pin = self.driver_insts[i].get_pin("br")
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# self.add_layout_pin(text="br_{0}".format(i),
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# layer="metal2",
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# offset=br_pin.ll(),
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# width=br_pin.width(),
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# height=br_pin.height())
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#
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# for n in ["vdd", "gnd"]:
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# pin_list = self.driver_insts[i].get_pins(n)
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# for pin in pin_list:
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# pin_pos = pin.center()
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# # Add the M2->M3 stack
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# self.add_via_center(layers=("metal2", "via2", "metal3"),
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# offset=pin_pos)
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# self.add_layout_pin_rect_center(text=n,
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# layer="metal3",
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# offset=pin_pos)
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#
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# self.add_layout_pin(text="en",
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# layer="metal1",
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# offset=self.driver_insts[0].get_pin("en").ll().scale(0, 1),
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# width=self.width,
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# height=drc('minwidth_metal1'))
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# def get_w_en_cin(self):
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# """Get the relative capacitance of all the enable connections in the bank"""
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# # The enable is connected to a nand2 for every row.
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# return self.driver.get_w_en_cin() * len(self.driver_insts)
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