mirror of https://github.com/VLSIDA/OpenRAM.git
Changed unit capacitance from CACTI estimation to PTM estimation.
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@ -425,7 +425,7 @@ spice["nom_temperature"] = 25 # Nominal temperature (celcius)
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# analytical delay parameters
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spice["nom_threshold"] = 0.4 # Typical Threshold voltage in Volts
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spice["wire_unit_r"] = 0.25 # Unit wire resistance in ohms/square
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spice["wire_unit_c"] = 2.3e-16 # Unit wire capacitance F/um^2, calculated from CACTI 45dat
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spice["wire_unit_c"] = 2.3e-15 # Unit wire capacitance F/um^2, calculated from PTM
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spice["min_tx_drain_c"] = 0.7 # Minimum transistor drain capacitance in ff
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spice["min_tx_gate_c"] = 0.2 # Minimum transistor gate capacitance in ff
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spice["dff_setup"] = 9 # DFF setup time in ps
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