mirror of https://github.com/VLSIDA/OpenRAM.git
fix dummy array opc
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parent
8eb6caa248
commit
ddb76c4aff
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@ -54,6 +54,8 @@ class sky130_dummy_array(sky130_bitcell_base_array):
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self.add_mod(self.strap2)
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self.add_mod(self.strap2)
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self.strap3 = factory.create(module_type="internal", version="wlstrapa")
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self.strap3 = factory.create(module_type="internal", version="wlstrapa")
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self.add_mod(self.strap3)
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self.add_mod(self.strap3)
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self.strap4 = factory.create(module_type="internal", version="wlstrapa_p")
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self.add_mod(self.strap4)
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self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
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self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
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def create_instances(self):
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def create_instances(self):
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@ -79,9 +81,14 @@ class sky130_dummy_array(sky130_bitcell_base_array):
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self.connect_inst(self.get_bitcell_pins(row, col))
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self.connect_inst(self.get_bitcell_pins(row, col))
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if col != self.column_size - 1:
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if col != self.column_size - 1:
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if alternate_strap:
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if alternate_strap:
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row_layout.append(self.strap2)
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if col % 2:
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self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col),
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row_layout.append(self.strap4)
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mod=self.strap2)
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self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col),
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mod=self.strap4)
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else:
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row_layout.append(self.strap4)
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self.add_inst(name="row_{}_col_{}_wlstrap".format(row, col),
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mod=self.strap4)
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alternate_strap = 0
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alternate_strap = 0
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else:
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else:
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if col % 2:
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if col % 2:
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