Change signal escape router's high-level function name

compiler/modules/sram_1bank.py

@@ -370,7 +370,7 @@ class sram_1bank(design, verilog, lef):
         rtr = router(layers=self.m3_stack,
                      design=self,
                      bbox=bbox)
-        rtr.escape_route(pins_to_route)
+        rtr.route(pins_to_route)
 
     def compute_bus_sizes(self):
         """ Compute the independent bus widths shared between two and four bank SRAMs """